Parallel processor and image processing apparatus
A global processor interprets a program and control entirety. A processor-element block includes a plurality of processor elements each comprising a register file and an operation array for processing a plurality of sets of data, wherein the global processor outputs a control signal to the plurality...
Gespeichert in:
Hauptverfasser: | , , , , |
---|---|
Format: | Patent |
Sprache: | eng |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | Yamaura, Shinichi Hara, Kazuhiko Katayama, Takao Iwanaga, Kazuhiko Takafuji, Hiroshi |
description | A global processor interprets a program and control entirety. A processor-element block includes a plurality of processor elements each comprising a register file and an operation array for processing a plurality of sets of data, wherein the global processor outputs a control signal to the plurality of processor elements, and, thereby, sets processor-element numbers corresponding to the plurality of processor elements as input values of the operation arrays, respectively. |
format | Patent |
fullrecord | <record><control><sourceid>uspatents_EFI</sourceid><recordid>TN_cdi_uspatents_applications_20010008563</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>20010008563</sourcerecordid><originalsourceid>FETCH-uspatents_applications_200100085633</originalsourceid><addsrcrecordid>eNrjZDAMSCxKzMlJzVEoKMpPTi0uzi9SSMxLUcjMTUxPhYll5qUrJBYUAFWWlBbzMLCmJeYUp_JCaW4GTTfXEGcP3dLigsSS1LyS4nig2pzM5MSSzPy84ngjAwNDAwMDC1MzY2NS1AIAGFIzCw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Parallel processor and image processing apparatus</title><source>USPTO Published Applications</source><creator>Yamaura, Shinichi ; Hara, Kazuhiko ; Katayama, Takao ; Iwanaga, Kazuhiko ; Takafuji, Hiroshi</creator><creatorcontrib>Yamaura, Shinichi ; Hara, Kazuhiko ; Katayama, Takao ; Iwanaga, Kazuhiko ; Takafuji, Hiroshi</creatorcontrib><description>A global processor interprets a program and control entirety. A processor-element block includes a plurality of processor elements each comprising a register file and an operation array for processing a plurality of sets of data, wherein the global processor outputs a control signal to the plurality of processor elements, and, thereby, sets processor-element numbers corresponding to the plurality of processor elements as input values of the operation arrays, respectively.</description><language>eng</language><creationdate>2001</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20010008563$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,776,869,881,64032</link.rule.ids><linktorsrc>$$Uhttps://patentcenter.uspto.gov/applications/09761122$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Yamaura, Shinichi</creatorcontrib><creatorcontrib>Hara, Kazuhiko</creatorcontrib><creatorcontrib>Katayama, Takao</creatorcontrib><creatorcontrib>Iwanaga, Kazuhiko</creatorcontrib><creatorcontrib>Takafuji, Hiroshi</creatorcontrib><title>Parallel processor and image processing apparatus</title><description>A global processor interprets a program and control entirety. A processor-element block includes a plurality of processor elements each comprising a register file and an operation array for processing a plurality of sets of data, wherein the global processor outputs a control signal to the plurality of processor elements, and, thereby, sets processor-element numbers corresponding to the plurality of processor elements as input values of the operation arrays, respectively.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2001</creationdate><recordtype>patent</recordtype><sourceid>EFI</sourceid><recordid>eNrjZDAMSCxKzMlJzVEoKMpPTi0uzi9SSMxLUcjMTUxPhYll5qUrJBYUAFWWlBbzMLCmJeYUp_JCaW4GTTfXEGcP3dLigsSS1LyS4nig2pzM5MSSzPy84ngjAwNDAwMDC1MzY2NS1AIAGFIzCw</recordid><startdate>20010719</startdate><enddate>20010719</enddate><creator>Yamaura, Shinichi</creator><creator>Hara, Kazuhiko</creator><creator>Katayama, Takao</creator><creator>Iwanaga, Kazuhiko</creator><creator>Takafuji, Hiroshi</creator><scope>EFI</scope></search><sort><creationdate>20010719</creationdate><title>Parallel processor and image processing apparatus</title><author>Yamaura, Shinichi ; Hara, Kazuhiko ; Katayama, Takao ; Iwanaga, Kazuhiko ; Takafuji, Hiroshi</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_applications_200100085633</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2001</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Yamaura, Shinichi</creatorcontrib><creatorcontrib>Hara, Kazuhiko</creatorcontrib><creatorcontrib>Katayama, Takao</creatorcontrib><creatorcontrib>Iwanaga, Kazuhiko</creatorcontrib><creatorcontrib>Takafuji, Hiroshi</creatorcontrib><collection>USPTO Published Applications</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Yamaura, Shinichi</au><au>Hara, Kazuhiko</au><au>Katayama, Takao</au><au>Iwanaga, Kazuhiko</au><au>Takafuji, Hiroshi</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Parallel processor and image processing apparatus</title><date>2001-07-19</date><risdate>2001</risdate><abstract>A global processor interprets a program and control entirety. A processor-element block includes a plurality of processor elements each comprising a register file and an operation array for processing a plurality of sets of data, wherein the global processor outputs a control signal to the plurality of processor elements, and, thereby, sets processor-element numbers corresponding to the plurality of processor elements as input values of the operation arrays, respectively.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng |
recordid | cdi_uspatents_applications_20010008563 |
source | USPTO Published Applications |
title | Parallel processor and image processing apparatus |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-11T23%3A40%3A10IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-uspatents_EFI&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Yamaura,%20Shinichi&rft.date=2001-07-19&rft_id=info:doi/&rft_dat=%3Cuspatents_EFI%3E20010008563%3C/uspatents_EFI%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |