GigaNetIC – A Scalable Embedded On-Chip Multiprocessor Architecture for Network Applications

In this paper, we present the prototypical implementation of the scalable GigaNetIC chip multiprocessor architecture. We use an FPGA-based rapid prototyping system to verify the functionality of our architecture in a network application scenario before we are going to fabricate the ASIC in a modern...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Niemann, Jörg-Christian, Puttmann, Christoph, Porrmann, Mario, Rückert, Ulrich
Format:	Buchkapitel
Sprache:	eng
Schlagworte:	Communication Controller Demonstrator System Hardware Accelerator Multiprocessor Architecture Processor Element
Online-Zugang:	Volltext
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