P-type NiOX dielectric-based CMOS inverter logic gate using enhancement-mode GaN nMOS and diamond pMOS transistors
We have demonstrated a complementary metal-oxide-semiconductor inverter logic gate by heterogeneous integration of an enhancement-mode n-channel transistor on GaN and a p-channel transistor on diamond. A thermally grown p-type NiOx is used as the dielectric, and Ni/Au is the gate metal for both tran...
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| Veröffentlicht in: | Applied physics letters 2024-12, Vol.125 (25) |
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| container_title | Applied physics letters |
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| creator | Patil, Mahalaxmi Pradhan, Subrat K. Shukla, Vivek K. Rai, Padmnabh Paul, Jayanti Sheikh, Aaqib H. Parvez, Bazila Ganguly, Swaroop Saha, Kasturi Saha, Dipankar |
| description | We have demonstrated a complementary metal-oxide-semiconductor inverter logic gate by heterogeneous integration of an enhancement-mode n-channel transistor on GaN and a p-channel transistor on diamond. A thermally grown p-type NiOx is used as the dielectric, and Ni/Au is the gate metal for both transistors. NiOx oxide on top of a partially recessed-gate AlGaN/GaN heterostructure depletes the two-dimensional electron gas by pulling the Fermi level closer to the valence band and making it normally OFF. The combination of Ni/NiOx gate metal work function and the dielectric helps to deplete the two-dimensional hole gas channel of a hydrogen-terminated p-channel diamond, making it an enhancement mode. The GaN n-MOS and diamond p-MOS transistors show output and transfer characteristics with threshold voltages of +0.6 and −1.2 V, respectively. nMOS and pMOS transistors show ION/IOFF current ratios of >105 and >103, respectively, with a subthreshold leakage of |
| doi_str_mv | 10.1063/5.0231002 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_scita</sourceid><recordid>TN_cdi_scitation_primary_10_1063_5_0231002</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>3145241142</sourcerecordid><originalsourceid>FETCH-LOGICAL-c1330-6f655c5bcfcadcf9dfc4efab8255ccaeb015c2ba2724f3c1232be3413ae19bc53</originalsourceid><addsrcrecordid>eNp9kE9LAzEUxIMoWKsHv0HAk0JqXrLpn6MUrUJtBRW8LdnsS03pJmuSCv32bmnPnoY3_GYeDCHXwAfAh_JeDbiQwLk4IT3goxGTAONT0uOcSzacKDgnFymtu1MJKXskvrG8a5Eu3PKL1g43aHJ0hlU6YU2nr8t36vwvxoyRbsLKGbrSGek2Ob-i6L-1N9igz6wJNdKZXlC_z2hfd226CZ22eyNH7ZNLOcR0Sc6s3iS8OmqffD49fkyf2Xw5e5k-zJkBKTkb2qFSRlXGGl0bO6mtKdDqaiw622isOCgjKi1GorDSgJCiQlmA1AiTyijZJzeH3jaGny2mXK7DNvruZSmhUKIAKERH3R4oE0NKEW3ZRtfouCuBl_tJS1UeJ-3YuwObjMs6u-D_gf8A1PJ2LA</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>3145241142</pqid></control><display><type>article</type><title>P-type NiOX dielectric-based CMOS inverter logic gate using enhancement-mode GaN nMOS and diamond pMOS transistors</title><source>AIP Journals Complete</source><creator>Patil, Mahalaxmi ; Pradhan, Subrat K. ; Shukla, Vivek K. ; Rai, Padmnabh ; Paul, Jayanti ; Sheikh, Aaqib H. ; Parvez, Bazila ; Ganguly, Swaroop ; Saha, Kasturi ; Saha, Dipankar</creator><creatorcontrib>Patil, Mahalaxmi ; Pradhan, Subrat K. ; Shukla, Vivek K. ; Rai, Padmnabh ; Paul, Jayanti ; Sheikh, Aaqib H. ; Parvez, Bazila ; Ganguly, Swaroop ; Saha, Kasturi ; Saha, Dipankar</creatorcontrib><description>We have demonstrated a complementary metal-oxide-semiconductor inverter logic gate by heterogeneous integration of an enhancement-mode n-channel transistor on GaN and a p-channel transistor on diamond. A thermally grown p-type NiOx is used as the dielectric, and Ni/Au is the gate metal for both transistors. NiOx oxide on top of a partially recessed-gate AlGaN/GaN heterostructure depletes the two-dimensional electron gas by pulling the Fermi level closer to the valence band and making it normally OFF. The combination of Ni/NiOx gate metal work function and the dielectric helps to deplete the two-dimensional hole gas channel of a hydrogen-terminated p-channel diamond, making it an enhancement mode. The GaN n-MOS and diamond p-MOS transistors show output and transfer characteristics with threshold voltages of +0.6 and −1.2 V, respectively. nMOS and pMOS transistors show ION/IOFF current ratios of >105 and >103, respectively, with a subthreshold leakage of <10 μA/mm. The gate current is negligible for both devices. The saturation drain current of the respective transistors is measured to be ∼170 and ∼20 mA/mm at a gate-to-source overdrive voltage of 3 V. The inverter input–output characteristics and transient response are measured for various rail-to-rail voltages and frequencies. The inverter threshold voltage is measured to be 1.1 V for a nominal operating voltage of 3 V.</description><identifier>ISSN: 0003-6951</identifier><identifier>EISSN: 1077-3118</identifier><identifier>DOI: 10.1063/5.0231002</identifier><identifier>CODEN: APPLAB</identifier><language>eng</language><publisher>Melville: American Institute of Physics</publisher><subject>Aluminum gallium nitrides ; CMOS ; Depletion ; Electron gas ; Gallium nitrides ; Gold ; Heterostructures ; Inverters ; Logic circuits ; Metal oxide semiconductors ; MOS devices ; Threshold voltage ; Transient response ; Transistors ; Valence band ; Work functions</subject><ispartof>Applied physics letters, 2024-12, Vol.125 (25)</ispartof><rights>Author(s)</rights><rights>2024 Author(s). Published under an exclusive license by AIP Publishing.</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><cites>FETCH-LOGICAL-c1330-6f655c5bcfcadcf9dfc4efab8255ccaeb015c2ba2724f3c1232be3413ae19bc53</cites><orcidid>0000-0003-4966-277X ; 0000-0002-3842-8884 ; 0000-0002-7157-9545 ; 0000-0002-2916-379X ; 0000-0002-5387-3388 ; 0000-0001-9954-9885 ; 0000-0003-4983-8974 ; 0000-0002-1491-5282 ; 0000-0003-1184-8421</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://pubs.aip.org/apl/article-lookup/doi/10.1063/5.0231002$$EHTML$$P50$$Gscitation$$H</linktohtml><link.rule.ids>314,780,784,794,4511,27923,27924,76255</link.rule.ids></links><search><creatorcontrib>Patil, Mahalaxmi</creatorcontrib><creatorcontrib>Pradhan, Subrat K.</creatorcontrib><creatorcontrib>Shukla, Vivek K.</creatorcontrib><creatorcontrib>Rai, Padmnabh</creatorcontrib><creatorcontrib>Paul, Jayanti</creatorcontrib><creatorcontrib>Sheikh, Aaqib H.</creatorcontrib><creatorcontrib>Parvez, Bazila</creatorcontrib><creatorcontrib>Ganguly, Swaroop</creatorcontrib><creatorcontrib>Saha, Kasturi</creatorcontrib><creatorcontrib>Saha, Dipankar</creatorcontrib><title>P-type NiOX dielectric-based CMOS inverter logic gate using enhancement-mode GaN nMOS and diamond pMOS transistors</title><title>Applied physics letters</title><description>We have demonstrated a complementary metal-oxide-semiconductor inverter logic gate by heterogeneous integration of an enhancement-mode n-channel transistor on GaN and a p-channel transistor on diamond. A thermally grown p-type NiOx is used as the dielectric, and Ni/Au is the gate metal for both transistors. NiOx oxide on top of a partially recessed-gate AlGaN/GaN heterostructure depletes the two-dimensional electron gas by pulling the Fermi level closer to the valence band and making it normally OFF. The combination of Ni/NiOx gate metal work function and the dielectric helps to deplete the two-dimensional hole gas channel of a hydrogen-terminated p-channel diamond, making it an enhancement mode. The GaN n-MOS and diamond p-MOS transistors show output and transfer characteristics with threshold voltages of +0.6 and −1.2 V, respectively. nMOS and pMOS transistors show ION/IOFF current ratios of >105 and >103, respectively, with a subthreshold leakage of <10 μA/mm. The gate current is negligible for both devices. The saturation drain current of the respective transistors is measured to be ∼170 and ∼20 mA/mm at a gate-to-source overdrive voltage of 3 V. The inverter input–output characteristics and transient response are measured for various rail-to-rail voltages and frequencies. The inverter threshold voltage is measured to be 1.1 V for a nominal operating voltage of 3 V.</description><subject>Aluminum gallium nitrides</subject><subject>CMOS</subject><subject>Depletion</subject><subject>Electron gas</subject><subject>Gallium nitrides</subject><subject>Gold</subject><subject>Heterostructures</subject><subject>Inverters</subject><subject>Logic circuits</subject><subject>Metal oxide semiconductors</subject><subject>MOS devices</subject><subject>Threshold voltage</subject><subject>Transient response</subject><subject>Transistors</subject><subject>Valence band</subject><subject>Work functions</subject><issn>0003-6951</issn><issn>1077-3118</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2024</creationdate><recordtype>article</recordtype><recordid>eNp9kE9LAzEUxIMoWKsHv0HAk0JqXrLpn6MUrUJtBRW8LdnsS03pJmuSCv32bmnPnoY3_GYeDCHXwAfAh_JeDbiQwLk4IT3goxGTAONT0uOcSzacKDgnFymtu1MJKXskvrG8a5Eu3PKL1g43aHJ0hlU6YU2nr8t36vwvxoyRbsLKGbrSGek2Ob-i6L-1N9igz6wJNdKZXlC_z2hfd226CZ22eyNH7ZNLOcR0Sc6s3iS8OmqffD49fkyf2Xw5e5k-zJkBKTkb2qFSRlXGGl0bO6mtKdDqaiw622isOCgjKi1GorDSgJCiQlmA1AiTyijZJzeH3jaGny2mXK7DNvruZSmhUKIAKERH3R4oE0NKEW3ZRtfouCuBl_tJS1UeJ-3YuwObjMs6u-D_gf8A1PJ2LA</recordid><startdate>20241216</startdate><enddate>20241216</enddate><creator>Patil, Mahalaxmi</creator><creator>Pradhan, Subrat K.</creator><creator>Shukla, Vivek K.</creator><creator>Rai, Padmnabh</creator><creator>Paul, Jayanti</creator><creator>Sheikh, Aaqib H.</creator><creator>Parvez, Bazila</creator><creator>Ganguly, Swaroop</creator><creator>Saha, Kasturi</creator><creator>Saha, Dipankar</creator><general>American Institute of Physics</general><scope>AAYXX</scope><scope>CITATION</scope><scope>8FD</scope><scope>H8D</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0003-4966-277X</orcidid><orcidid>https://orcid.org/0000-0002-3842-8884</orcidid><orcidid>https://orcid.org/0000-0002-7157-9545</orcidid><orcidid>https://orcid.org/0000-0002-2916-379X</orcidid><orcidid>https://orcid.org/0000-0002-5387-3388</orcidid><orcidid>https://orcid.org/0000-0001-9954-9885</orcidid><orcidid>https://orcid.org/0000-0003-4983-8974</orcidid><orcidid>https://orcid.org/0000-0002-1491-5282</orcidid><orcidid>https://orcid.org/0000-0003-1184-8421</orcidid></search><sort><creationdate>20241216</creationdate><title>P-type NiOX dielectric-based CMOS inverter logic gate using enhancement-mode GaN nMOS and diamond pMOS transistors</title><author>Patil, Mahalaxmi ; Pradhan, Subrat K. ; Shukla, Vivek K. ; Rai, Padmnabh ; Paul, Jayanti ; Sheikh, Aaqib H. ; Parvez, Bazila ; Ganguly, Swaroop ; Saha, Kasturi ; Saha, Dipankar</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c1330-6f655c5bcfcadcf9dfc4efab8255ccaeb015c2ba2724f3c1232be3413ae19bc53</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2024</creationdate><topic>Aluminum gallium nitrides</topic><topic>CMOS</topic><topic>Depletion</topic><topic>Electron gas</topic><topic>Gallium nitrides</topic><topic>Gold</topic><topic>Heterostructures</topic><topic>Inverters</topic><topic>Logic circuits</topic><topic>Metal oxide semiconductors</topic><topic>MOS devices</topic><topic>Threshold voltage</topic><topic>Transient response</topic><topic>Transistors</topic><topic>Valence band</topic><topic>Work functions</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Patil, Mahalaxmi</creatorcontrib><creatorcontrib>Pradhan, Subrat K.</creatorcontrib><creatorcontrib>Shukla, Vivek K.</creatorcontrib><creatorcontrib>Rai, Padmnabh</creatorcontrib><creatorcontrib>Paul, Jayanti</creatorcontrib><creatorcontrib>Sheikh, Aaqib H.</creatorcontrib><creatorcontrib>Parvez, Bazila</creatorcontrib><creatorcontrib>Ganguly, Swaroop</creatorcontrib><creatorcontrib>Saha, Kasturi</creatorcontrib><creatorcontrib>Saha, Dipankar</creatorcontrib><collection>CrossRef</collection><collection>Technology Research Database</collection><collection>Aerospace Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>Applied physics letters</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Patil, Mahalaxmi</au><au>Pradhan, Subrat K.</au><au>Shukla, Vivek K.</au><au>Rai, Padmnabh</au><au>Paul, Jayanti</au><au>Sheikh, Aaqib H.</au><au>Parvez, Bazila</au><au>Ganguly, Swaroop</au><au>Saha, Kasturi</au><au>Saha, Dipankar</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>P-type NiOX dielectric-based CMOS inverter logic gate using enhancement-mode GaN nMOS and diamond pMOS transistors</atitle><jtitle>Applied physics letters</jtitle><date>2024-12-16</date><risdate>2024</risdate><volume>125</volume><issue>25</issue><issn>0003-6951</issn><eissn>1077-3118</eissn><coden>APPLAB</coden><abstract>We have demonstrated a complementary metal-oxide-semiconductor inverter logic gate by heterogeneous integration of an enhancement-mode n-channel transistor on GaN and a p-channel transistor on diamond. A thermally grown p-type NiOx is used as the dielectric, and Ni/Au is the gate metal for both transistors. NiOx oxide on top of a partially recessed-gate AlGaN/GaN heterostructure depletes the two-dimensional electron gas by pulling the Fermi level closer to the valence band and making it normally OFF. The combination of Ni/NiOx gate metal work function and the dielectric helps to deplete the two-dimensional hole gas channel of a hydrogen-terminated p-channel diamond, making it an enhancement mode. The GaN n-MOS and diamond p-MOS transistors show output and transfer characteristics with threshold voltages of +0.6 and −1.2 V, respectively. nMOS and pMOS transistors show ION/IOFF current ratios of >105 and >103, respectively, with a subthreshold leakage of <10 μA/mm. The gate current is negligible for both devices. The saturation drain current of the respective transistors is measured to be ∼170 and ∼20 mA/mm at a gate-to-source overdrive voltage of 3 V. The inverter input–output characteristics and transient response are measured for various rail-to-rail voltages and frequencies. The inverter threshold voltage is measured to be 1.1 V for a nominal operating voltage of 3 V.</abstract><cop>Melville</cop><pub>American Institute of Physics</pub><doi>10.1063/5.0231002</doi><tpages>7</tpages><orcidid>https://orcid.org/0000-0003-4966-277X</orcidid><orcidid>https://orcid.org/0000-0002-3842-8884</orcidid><orcidid>https://orcid.org/0000-0002-7157-9545</orcidid><orcidid>https://orcid.org/0000-0002-2916-379X</orcidid><orcidid>https://orcid.org/0000-0002-5387-3388</orcidid><orcidid>https://orcid.org/0000-0001-9954-9885</orcidid><orcidid>https://orcid.org/0000-0003-4983-8974</orcidid><orcidid>https://orcid.org/0000-0002-1491-5282</orcidid><orcidid>https://orcid.org/0000-0003-1184-8421</orcidid></addata></record> |
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| language | eng |
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| source | AIP Journals Complete |
| subjects | Aluminum gallium nitrides CMOS Depletion Electron gas Gallium nitrides Gold Heterostructures Inverters Logic circuits Metal oxide semiconductors MOS devices Threshold voltage Transient response Transistors Valence band Work functions |
| title | P-type NiOX dielectric-based CMOS inverter logic gate using enhancement-mode GaN nMOS and diamond pMOS transistors |
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