FFT implementation of OFDM for future SG communication

Orthogonal multiplexing modulation introduces a significant amount of delay in massive multiple-output input (MIMO) systems. To meet the low latency need of large MIMO systems, a Fourier fast transformer (FFT) processor and associated reordering system are proposed, which decreases both the processing and reordering latency of OFDM-based systems. The primary objective is to minimize the number of computations required and, therefore, the processing time by utilizing OFDM guard bands. In the case of an FFT/IFFT employing CORDIC, the proposed approach may result in a reduction of around 2.4 percent of the total chip area. To do this, the restructured memory structure is constructed using modified pipeline architecture and the Cordic technique of effective memory. Using the CORDIC approach, an FFT/IFFT processor has been developed. It is developed in Verilog HDL and synthesized using Xilinx ISE 14.7.