A novel implementation of 4 bit parity generator in 7nm technology

In today’s low power designed life, the dissipated leakage power became as one of the tough task. This type of leakage power will reduced enormously with the threshold voltage scaling only. Along with power scaling, proper transmission of data is necessary without any noise or any other sort of disturbance. For that purpose, a parity generator is required to check the errors during transmission. So, a tough challenge is to design this type of even and odd parity generator with a low power and it was finally worked out in our paper using FINFET 7nm technology in EDA tool. The leakage current is the sum of source, drain and gate current and it is observed as 31.4nA in our paper. Along with these, frequency and delay using EDA (LTspice) tool in 7nm technology which reduces the leakage power drastically.