16×16 fast signed multiplier using Booth and Vedic architecture
This paper present the new 16×16 signed multiplier design using Booth architecture and Vedic architecture. The Booth architecture is based on Radix-4 Booth multiplier which reduces the number of partial product generated into almost half. Vedic architecture has advantages in partial product generati...
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creator | Shing, L. Z. Hussin, R. Kamarudin, A. Mohyar, S. N. Taking, S. Aziz, M. H. A. Ahmad, N. |
description | This paper present the new 16×16 signed multiplier design using Booth architecture and Vedic architecture. The Booth architecture is based on Radix-4 Booth multiplier which reduces the number of partial product generated into almost half. Vedic architecture has advantages in partial product generation and addition which are done concurrently [1]. In order to improved the performance of signed muliplier, the 16×16 signed multiplicand and multiplier is partition by using the 16×16 Vedic architecture (8 bits per block). Radix-4 Booth multiplier is used to multiply each block as in 16×16 Vedic architecture. This new 16×16 signed multiplier is taking advantages on Booth multiplier approach on top of Vedic achitecture. It has simple architecture compared to normal 16×16 Radix-4 Booth multiplier. This new signed multiplier uses Ripple Carry Adder (RCA) or Carry Look-Ahead Adder (CLA) to add up the generated partial product. This new 16×16 signed multiplier has improved the performance by reducing the total propagation delay. The new 16×16 signed multiplier design 1 (RCA) and design 2 (CLA) are 33.4% and 35.6% faster compared to the 16×16 Radix-4 Booth multiplier. It is because the partial product generation by Radix-4 Booth multiplier and partial product addition are done concurrently using Vedic architecture. |
doi_str_mv | 10.1063/1.5080898 |
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Z. ; Hussin, R. ; Kamarudin, A. ; Mohyar, S. N. ; Taking, S. ; Aziz, M. H. A. ; Ahmad, N.</creator><contributor>Ismail, Nur Syakimah ; Ramli, Muhammad Mahyiddin ; Wei-Wen, Liu ; Hong, Voon Chun ; Isa, Siti Salwa Mat ; Fathil, Mohamad Faris Mohamad</contributor><creatorcontrib>Shing, L. Z. ; Hussin, R. ; Kamarudin, A. ; Mohyar, S. N. ; Taking, S. ; Aziz, M. H. A. ; Ahmad, N. ; Ismail, Nur Syakimah ; Ramli, Muhammad Mahyiddin ; Wei-Wen, Liu ; Hong, Voon Chun ; Isa, Siti Salwa Mat ; Fathil, Mohamad Faris Mohamad</creatorcontrib><description>This paper present the new 16×16 signed multiplier design using Booth architecture and Vedic architecture. The Booth architecture is based on Radix-4 Booth multiplier which reduces the number of partial product generated into almost half. Vedic architecture has advantages in partial product generation and addition which are done concurrently [1]. In order to improved the performance of signed muliplier, the 16×16 signed multiplicand and multiplier is partition by using the 16×16 Vedic architecture (8 bits per block). Radix-4 Booth multiplier is used to multiply each block as in 16×16 Vedic architecture. This new 16×16 signed multiplier is taking advantages on Booth multiplier approach on top of Vedic achitecture. It has simple architecture compared to normal 16×16 Radix-4 Booth multiplier. This new signed multiplier uses Ripple Carry Adder (RCA) or Carry Look-Ahead Adder (CLA) to add up the generated partial product. This new 16×16 signed multiplier has improved the performance by reducing the total propagation delay. The new 16×16 signed multiplier design 1 (RCA) and design 2 (CLA) are 33.4% and 35.6% faster compared to the 16×16 Radix-4 Booth multiplier. It is because the partial product generation by Radix-4 Booth multiplier and partial product addition are done concurrently using Vedic architecture.</description><identifier>ISSN: 0094-243X</identifier><identifier>EISSN: 1551-7616</identifier><identifier>DOI: 10.1063/1.5080898</identifier><identifier>CODEN: APCPCS</identifier><language>eng</language><publisher>Melville: American Institute of Physics</publisher><subject>Adding circuits ; Architecture</subject><ispartof>AIP conference proceedings, 2018, Vol.2045 (1)</ispartof><rights>Author(s)</rights><rights>2018 Author(s). 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Z.</creatorcontrib><creatorcontrib>Hussin, R.</creatorcontrib><creatorcontrib>Kamarudin, A.</creatorcontrib><creatorcontrib>Mohyar, S. N.</creatorcontrib><creatorcontrib>Taking, S.</creatorcontrib><creatorcontrib>Aziz, M. H. A.</creatorcontrib><creatorcontrib>Ahmad, N.</creatorcontrib><title>16×16 fast signed multiplier using Booth and Vedic architecture</title><title>AIP conference proceedings</title><description>This paper present the new 16×16 signed multiplier design using Booth architecture and Vedic architecture. The Booth architecture is based on Radix-4 Booth multiplier which reduces the number of partial product generated into almost half. Vedic architecture has advantages in partial product generation and addition which are done concurrently [1]. In order to improved the performance of signed muliplier, the 16×16 signed multiplicand and multiplier is partition by using the 16×16 Vedic architecture (8 bits per block). Radix-4 Booth multiplier is used to multiply each block as in 16×16 Vedic architecture. This new 16×16 signed multiplier is taking advantages on Booth multiplier approach on top of Vedic achitecture. It has simple architecture compared to normal 16×16 Radix-4 Booth multiplier. This new signed multiplier uses Ripple Carry Adder (RCA) or Carry Look-Ahead Adder (CLA) to add up the generated partial product. This new 16×16 signed multiplier has improved the performance by reducing the total propagation delay. The new 16×16 signed multiplier design 1 (RCA) and design 2 (CLA) are 33.4% and 35.6% faster compared to the 16×16 Radix-4 Booth multiplier. It is because the partial product generation by Radix-4 Booth multiplier and partial product addition are done concurrently using Vedic architecture.</description><subject>Adding circuits</subject><subject>Architecture</subject><issn>0094-243X</issn><issn>1551-7616</issn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2018</creationdate><recordtype>conference_proceeding</recordtype><recordid>eNp9kMtKAzEYhYMoWKsL3yDgTpiaP5nJZecFb1Bwo-IuZCZJm9LOjElG8El8IF_MkRbcuTqbj_NxDkKnQGZAOLuAWUUkkUruoQlUFRSCA99HE0JUWdCSvR2io5RWhFAlhJygS-DfX8CxNynjFBats3gzrHPo18FFPKTQLvB11-UlNq3Fr86GBpvYLEN2TR6iO0YH3qyTO9nlFL3c3T7fPBTzp_vHm6t50YxWWRjZCCWsACtr72hdltRy4zmviawVMV4Q1VBpjXCMKemZc6yqK0-lgZoby6bobNvbx-59cCnrVTfEdlRqCuNmThWBkTrfUqkJ2eTQtbqPYWPipwaifx_SoHcP_Qd_dPEP1L317AdqT2aB</recordid><startdate>20181206</startdate><enddate>20181206</enddate><creator>Shing, L. Z.</creator><creator>Hussin, R.</creator><creator>Kamarudin, A.</creator><creator>Mohyar, S. N.</creator><creator>Taking, S.</creator><creator>Aziz, M. H. A.</creator><creator>Ahmad, N.</creator><general>American Institute of Physics</general><scope>8FD</scope><scope>H8D</scope><scope>L7M</scope></search><sort><creationdate>20181206</creationdate><title>16×16 fast signed multiplier using Booth and Vedic architecture</title><author>Shing, L. Z. ; Hussin, R. ; Kamarudin, A. ; Mohyar, S. N. ; Taking, S. ; Aziz, M. H. A. ; Ahmad, N.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c2438-a8c797d71d8bfe2b442d6af66b08b90af709c28da7e3398f3ee35b5f28a1b6ad3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2018</creationdate><topic>Adding circuits</topic><topic>Architecture</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Shing, L. Z.</creatorcontrib><creatorcontrib>Hussin, R.</creatorcontrib><creatorcontrib>Kamarudin, A.</creatorcontrib><creatorcontrib>Mohyar, S. N.</creatorcontrib><creatorcontrib>Taking, S.</creatorcontrib><creatorcontrib>Aziz, M. H. A.</creatorcontrib><creatorcontrib>Ahmad, N.</creatorcontrib><collection>Technology Research Database</collection><collection>Aerospace Database</collection><collection>Advanced Technologies Database with Aerospace</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Shing, L. Z.</au><au>Hussin, R.</au><au>Kamarudin, A.</au><au>Mohyar, S. N.</au><au>Taking, S.</au><au>Aziz, M. H. A.</au><au>Ahmad, N.</au><au>Ismail, Nur Syakimah</au><au>Ramli, Muhammad Mahyiddin</au><au>Wei-Wen, Liu</au><au>Hong, Voon Chun</au><au>Isa, Siti Salwa Mat</au><au>Fathil, Mohamad Faris Mohamad</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>16×16 fast signed multiplier using Booth and Vedic architecture</atitle><btitle>AIP conference proceedings</btitle><date>2018-12-06</date><risdate>2018</risdate><volume>2045</volume><issue>1</issue><issn>0094-243X</issn><eissn>1551-7616</eissn><coden>APCPCS</coden><abstract>This paper present the new 16×16 signed multiplier design using Booth architecture and Vedic architecture. The Booth architecture is based on Radix-4 Booth multiplier which reduces the number of partial product generated into almost half. Vedic architecture has advantages in partial product generation and addition which are done concurrently [1]. In order to improved the performance of signed muliplier, the 16×16 signed multiplicand and multiplier is partition by using the 16×16 Vedic architecture (8 bits per block). Radix-4 Booth multiplier is used to multiply each block as in 16×16 Vedic architecture. This new 16×16 signed multiplier is taking advantages on Booth multiplier approach on top of Vedic achitecture. It has simple architecture compared to normal 16×16 Radix-4 Booth multiplier. This new signed multiplier uses Ripple Carry Adder (RCA) or Carry Look-Ahead Adder (CLA) to add up the generated partial product. This new 16×16 signed multiplier has improved the performance by reducing the total propagation delay. The new 16×16 signed multiplier design 1 (RCA) and design 2 (CLA) are 33.4% and 35.6% faster compared to the 16×16 Radix-4 Booth multiplier. It is because the partial product generation by Radix-4 Booth multiplier and partial product addition are done concurrently using Vedic architecture.</abstract><cop>Melville</cop><pub>American Institute of Physics</pub><doi>10.1063/1.5080898</doi><tpages>8</tpages><oa>free_for_read</oa></addata></record> |
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subjects | Adding circuits Architecture |
title | 16×16 fast signed multiplier using Booth and Vedic architecture |
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