Characterization of floating-gate memory device with thiolate-protected gold and gold-palladium nanoclusters
The floating-gate memory characteristics of thiolate-protected gold (Au:SR) and palladium doped Au (AuPd:SR) nanoclusters, Au25(SR)18, Au24Pd(SR)18, and Au38(SR)24 (R = C12H25), were investigated by capacitance-voltage (C–V) measurements in vacuum. Monolayer films of Au:SR nanoclusters were formed a...
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| Veröffentlicht in: | AIP advances 2018-06, Vol.8 (6), p.065002-065002-9 |
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| creator | Yokoyama, Takaho Hirata, Naoyuki Tsunoyama, Hironori Negishi, Yuichi Nakajima, Atsushi |
| description | The floating-gate memory characteristics of thiolate-protected gold (Au:SR) and palladium doped Au (AuPd:SR) nanoclusters, Au25(SR)18, Au24Pd(SR)18, and Au38(SR)24 (R = C12H25), were investigated by capacitance-voltage (C–V) measurements in vacuum. Monolayer films of Au:SR nanoclusters were formed as floating-gate memory layers on p-type Si substrates by the Langmuir-Schaefer method with surface pressure − area (π-A) isotherm measurements. A fluoropolymer (CYTOP, ∼15 nm thick) was spin-coated on top to form a hydrophobic insulating layer. Using an Au pad (∼40 nm thick) as the gate electrode, C–V measurements exhibit clockwise hysteresis curves originating from the Au:SR and AuPd:SR nanoclusters against the reference measured in each sample, and the hysteresis widths were dependent on the composition and sizes of the Au:SR nanoclusters. The positive and negative voltage shifts in the hysteresis can be explained in terms of electronic structures in Au:SR and AuPd:SR-based devices. |
| doi_str_mv | 10.1063/1.5025509 |
| format | Article |
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Monolayer films of Au:SR nanoclusters were formed as floating-gate memory layers on p-type Si substrates by the Langmuir-Schaefer method with surface pressure − area (π-A) isotherm measurements. A fluoropolymer (CYTOP, ∼15 nm thick) was spin-coated on top to form a hydrophobic insulating layer. Using an Au pad (∼40 nm thick) as the gate electrode, C–V measurements exhibit clockwise hysteresis curves originating from the Au:SR and AuPd:SR nanoclusters against the reference measured in each sample, and the hysteresis widths were dependent on the composition and sizes of the Au:SR nanoclusters. The positive and negative voltage shifts in the hysteresis can be explained in terms of electronic structures in Au:SR and AuPd:SR-based devices.</description><identifier>ISSN: 2158-3226</identifier><identifier>EISSN: 2158-3226</identifier><identifier>DOI: 10.1063/1.5025509</identifier><identifier>CODEN: AAIDBI</identifier><language>eng</language><publisher>Melville: American Institute of Physics</publisher><subject>Electric potential ; Floating structures ; Fluoropolymers ; Gold ; Hysteresis ; Memory devices ; Nanoclusters ; Palladium ; Pressure ; Protective coatings ; Silicon substrates ; Spin coating</subject><ispartof>AIP advances, 2018-06, Vol.8 (6), p.065002-065002-9</ispartof><rights>Author(s)</rights><rights>2018 Author(s). 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Monolayer films of Au:SR nanoclusters were formed as floating-gate memory layers on p-type Si substrates by the Langmuir-Schaefer method with surface pressure − area (π-A) isotherm measurements. A fluoropolymer (CYTOP, ∼15 nm thick) was spin-coated on top to form a hydrophobic insulating layer. Using an Au pad (∼40 nm thick) as the gate electrode, C–V measurements exhibit clockwise hysteresis curves originating from the Au:SR and AuPd:SR nanoclusters against the reference measured in each sample, and the hysteresis widths were dependent on the composition and sizes of the Au:SR nanoclusters. The positive and negative voltage shifts in the hysteresis can be explained in terms of electronic structures in Au:SR and AuPd:SR-based devices.</description><subject>Electric potential</subject><subject>Floating structures</subject><subject>Fluoropolymers</subject><subject>Gold</subject><subject>Hysteresis</subject><subject>Memory devices</subject><subject>Nanoclusters</subject><subject>Palladium</subject><subject>Pressure</subject><subject>Protective coatings</subject><subject>Silicon substrates</subject><subject>Spin coating</subject><issn>2158-3226</issn><issn>2158-3226</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2018</creationdate><recordtype>article</recordtype><sourceid>DOA</sourceid><recordid>eNqdkU9rXCEUxR-lhYQ0i3wDoasWXuLfebosQ5sGAt20a7mj1xkH5zlVJyX99LV5oem6InrQn-eodxiuGL1mdCVu2LWiXClqXg3nnCk9Cs5Xr__RZ8NlrXvamzSMank-pPUOCriGJf6CFvNMciAh5a7n7biFhuSAh1weiceH6JD8jG1H2i7m1PfGY8kN-2lPtjl5AvMixiOkBD6eDmSGObt0qj2hvh3eBEgVL5_ni-H750_f1l_G-6-3d-uP96OTXLfRM60mJrB3J5XYaMZ54A6lMRSB9lEJuXEBfJhWbjJq8txopiYulDFGiIvhbvH1Gfb2WOIByqPNEO3TQi5bC6VFl9Aq3FATjJecUbmawoaiA_QTQ0mpAd-93i1e_ak_Tlib3edTmfv1Lada90SpeafeL5QrudaC4W8qo_ZPbSyzz7Xp7IeFrS62pz__P_ghlxfQHn0QvwFPcJ0R</recordid><startdate>201806</startdate><enddate>201806</enddate><creator>Yokoyama, Takaho</creator><creator>Hirata, Naoyuki</creator><creator>Tsunoyama, Hironori</creator><creator>Negishi, Yuichi</creator><creator>Nakajima, Atsushi</creator><general>American Institute of Physics</general><general>AIP Publishing LLC</general><scope>AJDQP</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>8FD</scope><scope>H8D</scope><scope>L7M</scope><scope>DOA</scope><orcidid>https://orcid.org/0000-0003-2650-5608</orcidid><orcidid>https://orcid.org/0000-0002-0332-5324</orcidid><orcidid>https://orcid.org/0000-0003-3965-1399</orcidid></search><sort><creationdate>201806</creationdate><title>Characterization of floating-gate memory device with thiolate-protected gold and gold-palladium nanoclusters</title><author>Yokoyama, Takaho ; Hirata, Naoyuki ; Tsunoyama, Hironori ; Negishi, Yuichi ; Nakajima, Atsushi</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c428t-d185713e13ec453b8122f2ce4990ea0990534bcfadf76c7957d29815723599933</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2018</creationdate><topic>Electric potential</topic><topic>Floating structures</topic><topic>Fluoropolymers</topic><topic>Gold</topic><topic>Hysteresis</topic><topic>Memory devices</topic><topic>Nanoclusters</topic><topic>Palladium</topic><topic>Pressure</topic><topic>Protective coatings</topic><topic>Silicon substrates</topic><topic>Spin coating</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Yokoyama, Takaho</creatorcontrib><creatorcontrib>Hirata, Naoyuki</creatorcontrib><creatorcontrib>Tsunoyama, Hironori</creatorcontrib><creatorcontrib>Negishi, Yuichi</creatorcontrib><creatorcontrib>Nakajima, Atsushi</creatorcontrib><collection>AIP Open Access Journals</collection><collection>CrossRef</collection><collection>Technology Research Database</collection><collection>Aerospace Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>DOAJ Directory of Open Access Journals</collection><jtitle>AIP advances</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Yokoyama, Takaho</au><au>Hirata, Naoyuki</au><au>Tsunoyama, Hironori</au><au>Negishi, Yuichi</au><au>Nakajima, Atsushi</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Characterization of floating-gate memory device with thiolate-protected gold and gold-palladium nanoclusters</atitle><jtitle>AIP advances</jtitle><date>2018-06</date><risdate>2018</risdate><volume>8</volume><issue>6</issue><spage>065002</spage><epage>065002-9</epage><pages>065002-065002-9</pages><issn>2158-3226</issn><eissn>2158-3226</eissn><coden>AAIDBI</coden><abstract>The floating-gate memory characteristics of thiolate-protected gold (Au:SR) and palladium doped Au (AuPd:SR) nanoclusters, Au25(SR)18, Au24Pd(SR)18, and Au38(SR)24 (R = C12H25), were investigated by capacitance-voltage (C–V) measurements in vacuum. Monolayer films of Au:SR nanoclusters were formed as floating-gate memory layers on p-type Si substrates by the Langmuir-Schaefer method with surface pressure − area (π-A) isotherm measurements. A fluoropolymer (CYTOP, ∼15 nm thick) was spin-coated on top to form a hydrophobic insulating layer. Using an Au pad (∼40 nm thick) as the gate electrode, C–V measurements exhibit clockwise hysteresis curves originating from the Au:SR and AuPd:SR nanoclusters against the reference measured in each sample, and the hysteresis widths were dependent on the composition and sizes of the Au:SR nanoclusters. The positive and negative voltage shifts in the hysteresis can be explained in terms of electronic structures in Au:SR and AuPd:SR-based devices.</abstract><cop>Melville</cop><pub>American Institute of Physics</pub><doi>10.1063/1.5025509</doi><tpages>9</tpages><orcidid>https://orcid.org/0000-0003-2650-5608</orcidid><orcidid>https://orcid.org/0000-0002-0332-5324</orcidid><orcidid>https://orcid.org/0000-0003-3965-1399</orcidid><oa>free_for_read</oa></addata></record> |
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| subjects | Electric potential Floating structures Fluoropolymers Gold Hysteresis Memory devices Nanoclusters Palladium Pressure Protective coatings Silicon substrates Spin coating |
| title | Characterization of floating-gate memory device with thiolate-protected gold and gold-palladium nanoclusters |
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