Gate-all-around junctionless silicon transistors with atomically thin nanosheet channel (0.65 nm) and record sub-threshold slope (43 mV/dec)
A silicon junctionless (JL) trench gate-all-around (GAA) nanowire field-effect transistor with an atomically thin channel thickness of 0.65 nm and a very thin oxide with a thickness of 12.3 nm are demonstrated experimentally. Experimental results indicate that this device with a channel thickness of...
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| Veröffentlicht in: | Applied physics letters 2017-01, Vol.110 (3) |
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| container_title | Applied physics letters |
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| creator | Thirunavukkarasu, Vasanthan Jhan, Yi-Ruei Liu, Yan-Bo Kurniawan, Erry Dwi Lin, Yu Ru Yang, Shang-Yi Cheng, Che-Hsiang Wu, Yung-Chun |
| description | A silicon junctionless (JL) trench gate-all-around (GAA) nanowire field-effect transistor with an atomically thin channel thickness of 0.65 nm and a very thin oxide with a thickness of 12.3 nm are demonstrated experimentally. Experimental results indicate that this device with a channel thickness of 0.65 nm achieves a sub-threshold slope (SS) of 43 mV/decade, which is the best yet achieved by any reported JLFET. Owing to the atomically thin channel, this device has an extremely high ION/IOFF current ratio of >108. Furthermore, the atomically thin channel GAA JLFET exhibits a low threshold voltage (VTH) variation and negligible drain-induced barrier lowering (DIBL |
| doi_str_mv | 10.1063/1.4974255 |
| format | Article |
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Experimental results indicate that this device with a channel thickness of 0.65 nm achieves a sub-threshold slope (SS) of 43 mV/decade, which is the best yet achieved by any reported JLFET. Owing to the atomically thin channel, this device has an extremely high ION/IOFF current ratio of >108. Furthermore, the atomically thin channel GAA JLFET exhibits a low threshold voltage (VTH) variation and negligible drain-induced barrier lowering (DIBL < 0.4 mV/V). The reported device with the thinnest channel has a very high band-to-band tunneling generation rate of 1.2 × 1024/cm2 s when the channel is scaled down to <1 nm, as confirmed by using the 3D quantum transport simulation tool. This quantum tunneling provides a means of achieving an SS value much lower than its fundamental physical limit.</description><identifier>ISSN: 0003-6951</identifier><identifier>EISSN: 1077-3118</identifier><identifier>DOI: 10.1063/1.4974255</identifier><identifier>CODEN: APPLAB</identifier><language>eng</language><publisher>Melville: American Institute of Physics</publisher><subject>Applied physics ; Field effect transistors ; Nanosheets ; Nanowires ; Quantum transport ; Quantum tunnelling ; Semiconductor devices ; Silicon transistors ; Threshold voltage</subject><ispartof>Applied physics letters, 2017-01, Vol.110 (3)</ispartof><rights>Author(s)</rights><rights>2017 Author(s). Published by AIP Publishing.</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c327t-21613eba620ef2b3fa70b8e8d5bb15eb326c0471adc446c82349cf84a11474563</citedby><cites>FETCH-LOGICAL-c327t-21613eba620ef2b3fa70b8e8d5bb15eb326c0471adc446c82349cf84a11474563</cites><orcidid>0000-0002-9976-5657 ; 0000-0002-9306-9474 ; 0000-0001-9409-6792</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://pubs.aip.org/apl/article-lookup/doi/10.1063/1.4974255$$EHTML$$P50$$Gscitation$$H</linktohtml><link.rule.ids>314,777,781,791,4498,27905,27906,76133</link.rule.ids></links><search><creatorcontrib>Thirunavukkarasu, Vasanthan</creatorcontrib><creatorcontrib>Jhan, Yi-Ruei</creatorcontrib><creatorcontrib>Liu, Yan-Bo</creatorcontrib><creatorcontrib>Kurniawan, Erry Dwi</creatorcontrib><creatorcontrib>Lin, Yu Ru</creatorcontrib><creatorcontrib>Yang, Shang-Yi</creatorcontrib><creatorcontrib>Cheng, Che-Hsiang</creatorcontrib><creatorcontrib>Wu, Yung-Chun</creatorcontrib><title>Gate-all-around junctionless silicon transistors with atomically thin nanosheet channel (0.65 nm) and record sub-threshold slope (43 mV/dec)</title><title>Applied physics letters</title><description>A silicon junctionless (JL) trench gate-all-around (GAA) nanowire field-effect transistor with an atomically thin channel thickness of 0.65 nm and a very thin oxide with a thickness of 12.3 nm are demonstrated experimentally. Experimental results indicate that this device with a channel thickness of 0.65 nm achieves a sub-threshold slope (SS) of 43 mV/decade, which is the best yet achieved by any reported JLFET. Owing to the atomically thin channel, this device has an extremely high ION/IOFF current ratio of >108. Furthermore, the atomically thin channel GAA JLFET exhibits a low threshold voltage (VTH) variation and negligible drain-induced barrier lowering (DIBL < 0.4 mV/V). The reported device with the thinnest channel has a very high band-to-band tunneling generation rate of 1.2 × 1024/cm2 s when the channel is scaled down to <1 nm, as confirmed by using the 3D quantum transport simulation tool. This quantum tunneling provides a means of achieving an SS value much lower than its fundamental physical limit.</description><subject>Applied physics</subject><subject>Field effect transistors</subject><subject>Nanosheets</subject><subject>Nanowires</subject><subject>Quantum transport</subject><subject>Quantum tunnelling</subject><subject>Semiconductor devices</subject><subject>Silicon transistors</subject><subject>Threshold voltage</subject><issn>0003-6951</issn><issn>1077-3118</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2017</creationdate><recordtype>article</recordtype><recordid>eNqdkM1KAzEUhYMoWKsL3yDgphWmze_MdCmiVSi4Ubchk8kwKTNJTTJKd27d-Yw-iSktuHd1OfCdc-ED4BKjGUY5neMZWxSMcH4ERhgVRUYxLo_BCCFEs3zB8Sk4C2GdIieUjsD3Ukadya7LpHeDreF6sCoaZzsdAgymM8pZGL20wYTofIAfJrZQRtcblWpbGFtjoZXWhVbrCFUrrdUdnKBZzn8-v2w_hTLteq2cr2EYqiy2XofWdSl1bqPhhNEE9q_zWqvpOThpZBf0xeGOwcv93fPtQ7Z6Wj7e3qwyRUkRM4JzTHUlc4J0QyrayAJVpS5rXlWY64qSXCFWYFkrxnJVEsoWqimZxJgVjOd0DK72uxvv3gYdoli7wdv0UhBMWFKFCpSo6Z5S3oXgdSM23vTSbwVGYidcYHEQntjrPRuUiXLn8H_wu_N_oNjUDf0F9VeRIQ</recordid><startdate>20170116</startdate><enddate>20170116</enddate><creator>Thirunavukkarasu, Vasanthan</creator><creator>Jhan, Yi-Ruei</creator><creator>Liu, Yan-Bo</creator><creator>Kurniawan, Erry Dwi</creator><creator>Lin, Yu Ru</creator><creator>Yang, Shang-Yi</creator><creator>Cheng, Che-Hsiang</creator><creator>Wu, Yung-Chun</creator><general>American Institute of Physics</general><scope>AAYXX</scope><scope>CITATION</scope><scope>8FD</scope><scope>H8D</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0002-9976-5657</orcidid><orcidid>https://orcid.org/0000-0002-9306-9474</orcidid><orcidid>https://orcid.org/0000-0001-9409-6792</orcidid></search><sort><creationdate>20170116</creationdate><title>Gate-all-around junctionless silicon transistors with atomically thin nanosheet channel (0.65 nm) and record sub-threshold slope (43 mV/dec)</title><author>Thirunavukkarasu, Vasanthan ; Jhan, Yi-Ruei ; Liu, Yan-Bo ; Kurniawan, Erry Dwi ; Lin, Yu Ru ; Yang, Shang-Yi ; Cheng, Che-Hsiang ; Wu, Yung-Chun</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c327t-21613eba620ef2b3fa70b8e8d5bb15eb326c0471adc446c82349cf84a11474563</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2017</creationdate><topic>Applied physics</topic><topic>Field effect transistors</topic><topic>Nanosheets</topic><topic>Nanowires</topic><topic>Quantum transport</topic><topic>Quantum tunnelling</topic><topic>Semiconductor devices</topic><topic>Silicon transistors</topic><topic>Threshold voltage</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Thirunavukkarasu, Vasanthan</creatorcontrib><creatorcontrib>Jhan, Yi-Ruei</creatorcontrib><creatorcontrib>Liu, Yan-Bo</creatorcontrib><creatorcontrib>Kurniawan, Erry Dwi</creatorcontrib><creatorcontrib>Lin, Yu Ru</creatorcontrib><creatorcontrib>Yang, Shang-Yi</creatorcontrib><creatorcontrib>Cheng, Che-Hsiang</creatorcontrib><creatorcontrib>Wu, Yung-Chun</creatorcontrib><collection>CrossRef</collection><collection>Technology Research Database</collection><collection>Aerospace Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>Applied physics letters</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Thirunavukkarasu, Vasanthan</au><au>Jhan, Yi-Ruei</au><au>Liu, Yan-Bo</au><au>Kurniawan, Erry Dwi</au><au>Lin, Yu Ru</au><au>Yang, Shang-Yi</au><au>Cheng, Che-Hsiang</au><au>Wu, Yung-Chun</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Gate-all-around junctionless silicon transistors with atomically thin nanosheet channel (0.65 nm) and record sub-threshold slope (43 mV/dec)</atitle><jtitle>Applied physics letters</jtitle><date>2017-01-16</date><risdate>2017</risdate><volume>110</volume><issue>3</issue><issn>0003-6951</issn><eissn>1077-3118</eissn><coden>APPLAB</coden><abstract>A silicon junctionless (JL) trench gate-all-around (GAA) nanowire field-effect transistor with an atomically thin channel thickness of 0.65 nm and a very thin oxide with a thickness of 12.3 nm are demonstrated experimentally. Experimental results indicate that this device with a channel thickness of 0.65 nm achieves a sub-threshold slope (SS) of 43 mV/decade, which is the best yet achieved by any reported JLFET. Owing to the atomically thin channel, this device has an extremely high ION/IOFF current ratio of >108. Furthermore, the atomically thin channel GAA JLFET exhibits a low threshold voltage (VTH) variation and negligible drain-induced barrier lowering (DIBL < 0.4 mV/V). The reported device with the thinnest channel has a very high band-to-band tunneling generation rate of 1.2 × 1024/cm2 s when the channel is scaled down to <1 nm, as confirmed by using the 3D quantum transport simulation tool. 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| source | AIP Journals Complete; Alma/SFX Local Collection |
| subjects | Applied physics Field effect transistors Nanosheets Nanowires Quantum transport Quantum tunnelling Semiconductor devices Silicon transistors Threshold voltage |
| title | Gate-all-around junctionless silicon transistors with atomically thin nanosheet channel (0.65 nm) and record sub-threshold slope (43 mV/dec) |
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