Stateful Three-Input Logic with Memristive Switches
Memristive switches are able to act as both storage and computing elements, which make them an excellent candidate for beyond-CMOS computing. In this paper, multi-input memristive switch logic is proposed, which enables the function X OR (Y NOR Z) to be performed in a single-step with three memristi...
Gespeichert in:
Veröffentlicht in: | Scientific reports 2019-10, Vol.9 (1), p.14618-13, Article 14618 |
---|---|
Hauptverfasser: | , , , , , , , , , |
Format: | Artikel |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | 13 |
---|---|
container_issue | 1 |
container_start_page | 14618 |
container_title | Scientific reports |
container_volume | 9 |
creator | Siemon, A. Drabinski, R. Schultis, M. J. Hu, X. Linn, E. Heittmann, A. Waser, R. Querlioz, D. Menzel, S. Friedman, J. S. |
description | Memristive switches are able to act as both storage and computing elements, which make them an excellent candidate for beyond-CMOS computing. In this paper, multi-input memristive switch logic is proposed, which enables the function X OR (Y NOR Z) to be performed in a single-step with three memristive switches. This ORNOR logic gate increases the capabilities of memristive switches, improving the overall system efficiency of a memristive switch-based computing architecture. Additionally, a computing system architecture and clocking scheme are proposed to further utilize memristive switching for computation. The system architecture is based on a design where multiple computational function blocks are interconnected and controlled by a master clock that synchronizes system data processing and transfer. The clocking steps to perform a full adder with the ORNOR gate are presented along with simulation results using a physics-based model. The full adder function block is integrated into the system architecture to realize a 64-bit full adder, which is also demonstrated through simulation. |
doi_str_mv | 10.1038/s41598-019-51039-6 |
format | Article |
fullrecord | <record><control><sourceid>proquest_pubme</sourceid><recordid>TN_cdi_pubmedcentral_primary_oai_pubmedcentral_nih_gov_6787102</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>2303724896</sourcerecordid><originalsourceid>FETCH-LOGICAL-c508t-f57cda8a03a6a2c5235af987c15ebcb158bcc91294820b29045f0e8fb0284cd83</originalsourceid><addsrcrecordid>eNp9kT1PwzAQhi0Eggr4AwwoEgsMgbMdJ_aCVFV8VApiAGbLcZ0mVZoUOyni3-OQ8tUBL7bunnvvzi9CJxguMVB-5SLMBA8Bi5D5gAjjHTQiELGQUEJ2f70P0LFzC_CHERFhsY8OKI6BANARok-tak3eVcFzYY0Jp_Wqa4O0mZc6eCvbIngwS1u6tlyb4MkHdGHcEdrLVeXM8eY-RC-3N8-T-zB9vJtOxmmoGfA2zFmiZ4oroCpWRDNCmcoFTzRmJtMZZjzTWmA_EyeQEeHnzcHwPAPCIz3j9BBdD7qrLluamTZ1a1UlV7ZcKvsuG1XKv5m6LOS8Wcs44QkG4gUuBoFiq-x-nMo-BhQiTKJkjT17vmlmm9fOuFYuS6dNVanaNJ2ThAKDiAOnHj3bQhdNZ2v_FT1FExJxEXuKDJS2jXPW5N8TYJC9hXKwUHoL5aeFsi86_b3yd8mXYR6gA-B8qp4b-9P7H9kPH86k6A</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>2303724896</pqid></control><display><type>article</type><title>Stateful Three-Input Logic with Memristive Switches</title><source>DOAJ Directory of Open Access Journals</source><source>Springer Nature OA Free Journals</source><source>Nature Free</source><source>EZB-FREE-00999 freely available EZB journals</source><source>PubMed Central</source><source>Free Full-Text Journals in Chemistry</source><creator>Siemon, A. ; Drabinski, R. ; Schultis, M. J. ; Hu, X. ; Linn, E. ; Heittmann, A. ; Waser, R. ; Querlioz, D. ; Menzel, S. ; Friedman, J. S.</creator><creatorcontrib>Siemon, A. ; Drabinski, R. ; Schultis, M. J. ; Hu, X. ; Linn, E. ; Heittmann, A. ; Waser, R. ; Querlioz, D. ; Menzel, S. ; Friedman, J. S.</creatorcontrib><description>Memristive switches are able to act as both storage and computing elements, which make them an excellent candidate for beyond-CMOS computing. In this paper, multi-input memristive switch logic is proposed, which enables the function X OR (Y NOR Z) to be performed in a single-step with three memristive switches. This ORNOR logic gate increases the capabilities of memristive switches, improving the overall system efficiency of a memristive switch-based computing architecture. Additionally, a computing system architecture and clocking scheme are proposed to further utilize memristive switching for computation. The system architecture is based on a design where multiple computational function blocks are interconnected and controlled by a master clock that synchronizes system data processing and transfer. The clocking steps to perform a full adder with the ORNOR gate are presented along with simulation results using a physics-based model. The full adder function block is integrated into the system architecture to realize a 64-bit full adder, which is also demonstrated through simulation.</description><identifier>ISSN: 2045-2322</identifier><identifier>EISSN: 2045-2322</identifier><identifier>DOI: 10.1038/s41598-019-51039-6</identifier><identifier>PMID: 31602003</identifier><language>eng</language><publisher>London: Nature Publishing Group UK</publisher><subject>119/118 ; 639/166/987 ; 639/925/927/1007 ; Computer applications ; Data processing ; Engineering Sciences ; Humanities and Social Sciences ; Logic ; multidisciplinary ; Science ; Science (multidisciplinary) ; Simulation</subject><ispartof>Scientific reports, 2019-10, Vol.9 (1), p.14618-13, Article 14618</ispartof><rights>The Author(s) 2019</rights><rights>2019. This work is published under http://creativecommons.org/licenses/by/4.0/ (the “License”). Notwithstanding the ProQuest Terms and Conditions, you may use this content in accordance with the terms of the License.</rights><rights>Distributed under a Creative Commons Attribution 4.0 International License</rights><lds50>peer_reviewed</lds50><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c508t-f57cda8a03a6a2c5235af987c15ebcb158bcc91294820b29045f0e8fb0284cd83</citedby><cites>FETCH-LOGICAL-c508t-f57cda8a03a6a2c5235af987c15ebcb158bcc91294820b29045f0e8fb0284cd83</cites><orcidid>0000-0002-7337-6637 ; 0000-0002-5426-9967 ; 0000-0001-9847-4455 ; 0000-0002-4258-2673</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://www.ncbi.nlm.nih.gov/pmc/articles/PMC6787102/pdf/$$EPDF$$P50$$Gpubmedcentral$$Hfree_for_read</linktopdf><linktohtml>$$Uhttps://www.ncbi.nlm.nih.gov/pmc/articles/PMC6787102/$$EHTML$$P50$$Gpubmedcentral$$Hfree_for_read</linktohtml><link.rule.ids>230,314,727,780,784,864,885,27924,27925,41120,42189,51576,53791,53793</link.rule.ids><backlink>$$Uhttps://www.ncbi.nlm.nih.gov/pubmed/31602003$$D View this record in MEDLINE/PubMed$$Hfree_for_read</backlink><backlink>$$Uhttps://hal.science/hal-03041247$$DView record in HAL$$Hfree_for_read</backlink></links><search><creatorcontrib>Siemon, A.</creatorcontrib><creatorcontrib>Drabinski, R.</creatorcontrib><creatorcontrib>Schultis, M. J.</creatorcontrib><creatorcontrib>Hu, X.</creatorcontrib><creatorcontrib>Linn, E.</creatorcontrib><creatorcontrib>Heittmann, A.</creatorcontrib><creatorcontrib>Waser, R.</creatorcontrib><creatorcontrib>Querlioz, D.</creatorcontrib><creatorcontrib>Menzel, S.</creatorcontrib><creatorcontrib>Friedman, J. S.</creatorcontrib><title>Stateful Three-Input Logic with Memristive Switches</title><title>Scientific reports</title><addtitle>Sci Rep</addtitle><addtitle>Sci Rep</addtitle><description>Memristive switches are able to act as both storage and computing elements, which make them an excellent candidate for beyond-CMOS computing. In this paper, multi-input memristive switch logic is proposed, which enables the function X OR (Y NOR Z) to be performed in a single-step with three memristive switches. This ORNOR logic gate increases the capabilities of memristive switches, improving the overall system efficiency of a memristive switch-based computing architecture. Additionally, a computing system architecture and clocking scheme are proposed to further utilize memristive switching for computation. The system architecture is based on a design where multiple computational function blocks are interconnected and controlled by a master clock that synchronizes system data processing and transfer. The clocking steps to perform a full adder with the ORNOR gate are presented along with simulation results using a physics-based model. The full adder function block is integrated into the system architecture to realize a 64-bit full adder, which is also demonstrated through simulation.</description><subject>119/118</subject><subject>639/166/987</subject><subject>639/925/927/1007</subject><subject>Computer applications</subject><subject>Data processing</subject><subject>Engineering Sciences</subject><subject>Humanities and Social Sciences</subject><subject>Logic</subject><subject>multidisciplinary</subject><subject>Science</subject><subject>Science (multidisciplinary)</subject><subject>Simulation</subject><issn>2045-2322</issn><issn>2045-2322</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2019</creationdate><recordtype>article</recordtype><sourceid>C6C</sourceid><sourceid>ABUWG</sourceid><sourceid>AFKRA</sourceid><sourceid>AZQEC</sourceid><sourceid>BENPR</sourceid><sourceid>CCPQU</sourceid><sourceid>DWQXO</sourceid><sourceid>GNUQQ</sourceid><recordid>eNp9kT1PwzAQhi0Eggr4AwwoEgsMgbMdJ_aCVFV8VApiAGbLcZ0mVZoUOyni3-OQ8tUBL7bunnvvzi9CJxguMVB-5SLMBA8Bi5D5gAjjHTQiELGQUEJ2f70P0LFzC_CHERFhsY8OKI6BANARok-tak3eVcFzYY0Jp_Wqa4O0mZc6eCvbIngwS1u6tlyb4MkHdGHcEdrLVeXM8eY-RC-3N8-T-zB9vJtOxmmoGfA2zFmiZ4oroCpWRDNCmcoFTzRmJtMZZjzTWmA_EyeQEeHnzcHwPAPCIz3j9BBdD7qrLluamTZ1a1UlV7ZcKvsuG1XKv5m6LOS8Wcs44QkG4gUuBoFiq-x-nMo-BhQiTKJkjT17vmlmm9fOuFYuS6dNVanaNJ2ThAKDiAOnHj3bQhdNZ2v_FT1FExJxEXuKDJS2jXPW5N8TYJC9hXKwUHoL5aeFsi86_b3yd8mXYR6gA-B8qp4b-9P7H9kPH86k6A</recordid><startdate>20191010</startdate><enddate>20191010</enddate><creator>Siemon, A.</creator><creator>Drabinski, R.</creator><creator>Schultis, M. J.</creator><creator>Hu, X.</creator><creator>Linn, E.</creator><creator>Heittmann, A.</creator><creator>Waser, R.</creator><creator>Querlioz, D.</creator><creator>Menzel, S.</creator><creator>Friedman, J. S.</creator><general>Nature Publishing Group UK</general><general>Nature Publishing Group</general><scope>C6C</scope><scope>NPM</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>3V.</scope><scope>7X7</scope><scope>7XB</scope><scope>88A</scope><scope>88E</scope><scope>88I</scope><scope>8FE</scope><scope>8FH</scope><scope>8FI</scope><scope>8FJ</scope><scope>8FK</scope><scope>ABUWG</scope><scope>AFKRA</scope><scope>AZQEC</scope><scope>BBNVY</scope><scope>BENPR</scope><scope>BHPHI</scope><scope>CCPQU</scope><scope>DWQXO</scope><scope>FYUFA</scope><scope>GHDGH</scope><scope>GNUQQ</scope><scope>HCIFZ</scope><scope>K9.</scope><scope>LK8</scope><scope>M0S</scope><scope>M1P</scope><scope>M2P</scope><scope>M7P</scope><scope>PIMPY</scope><scope>PQEST</scope><scope>PQQKQ</scope><scope>PQUKI</scope><scope>Q9U</scope><scope>7X8</scope><scope>1XC</scope><scope>VOOES</scope><scope>5PM</scope><orcidid>https://orcid.org/0000-0002-7337-6637</orcidid><orcidid>https://orcid.org/0000-0002-5426-9967</orcidid><orcidid>https://orcid.org/0000-0001-9847-4455</orcidid><orcidid>https://orcid.org/0000-0002-4258-2673</orcidid></search><sort><creationdate>20191010</creationdate><title>Stateful Three-Input Logic with Memristive Switches</title><author>Siemon, A. ; Drabinski, R. ; Schultis, M. J. ; Hu, X. ; Linn, E. ; Heittmann, A. ; Waser, R. ; Querlioz, D. ; Menzel, S. ; Friedman, J. S.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c508t-f57cda8a03a6a2c5235af987c15ebcb158bcc91294820b29045f0e8fb0284cd83</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2019</creationdate><topic>119/118</topic><topic>639/166/987</topic><topic>639/925/927/1007</topic><topic>Computer applications</topic><topic>Data processing</topic><topic>Engineering Sciences</topic><topic>Humanities and Social Sciences</topic><topic>Logic</topic><topic>multidisciplinary</topic><topic>Science</topic><topic>Science (multidisciplinary)</topic><topic>Simulation</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Siemon, A.</creatorcontrib><creatorcontrib>Drabinski, R.</creatorcontrib><creatorcontrib>Schultis, M. J.</creatorcontrib><creatorcontrib>Hu, X.</creatorcontrib><creatorcontrib>Linn, E.</creatorcontrib><creatorcontrib>Heittmann, A.</creatorcontrib><creatorcontrib>Waser, R.</creatorcontrib><creatorcontrib>Querlioz, D.</creatorcontrib><creatorcontrib>Menzel, S.</creatorcontrib><creatorcontrib>Friedman, J. S.</creatorcontrib><collection>Springer Nature OA Free Journals</collection><collection>PubMed</collection><collection>CrossRef</collection><collection>ProQuest Central (Corporate)</collection><collection>Health & Medical Collection</collection><collection>ProQuest Central (purchase pre-March 2016)</collection><collection>Biology Database (Alumni Edition)</collection><collection>Medical Database (Alumni Edition)</collection><collection>Science Database (Alumni Edition)</collection><collection>ProQuest SciTech Collection</collection><collection>ProQuest Natural Science Collection</collection><collection>Hospital Premium Collection</collection><collection>Hospital Premium Collection (Alumni Edition)</collection><collection>ProQuest Central (Alumni) (purchase pre-March 2016)</collection><collection>ProQuest Central (Alumni Edition)</collection><collection>ProQuest Central UK/Ireland</collection><collection>ProQuest Central Essentials</collection><collection>Biological Science Collection</collection><collection>ProQuest Central</collection><collection>Natural Science Collection</collection><collection>ProQuest One Community College</collection><collection>ProQuest Central Korea</collection><collection>Health Research Premium Collection</collection><collection>Health Research Premium Collection (Alumni)</collection><collection>ProQuest Central Student</collection><collection>SciTech Premium Collection</collection><collection>ProQuest Health & Medical Complete (Alumni)</collection><collection>ProQuest Biological Science Collection</collection><collection>Health & Medical Collection (Alumni Edition)</collection><collection>Medical Database</collection><collection>Science Database</collection><collection>Biological Science Database</collection><collection>Access via ProQuest (Open Access)</collection><collection>ProQuest One Academic Eastern Edition (DO NOT USE)</collection><collection>ProQuest One Academic</collection><collection>ProQuest One Academic UKI Edition</collection><collection>ProQuest Central Basic</collection><collection>MEDLINE - Academic</collection><collection>Hyper Article en Ligne (HAL)</collection><collection>Hyper Article en Ligne (HAL) (Open Access)</collection><collection>PubMed Central (Full Participant titles)</collection><jtitle>Scientific reports</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Siemon, A.</au><au>Drabinski, R.</au><au>Schultis, M. J.</au><au>Hu, X.</au><au>Linn, E.</au><au>Heittmann, A.</au><au>Waser, R.</au><au>Querlioz, D.</au><au>Menzel, S.</au><au>Friedman, J. S.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Stateful Three-Input Logic with Memristive Switches</atitle><jtitle>Scientific reports</jtitle><stitle>Sci Rep</stitle><addtitle>Sci Rep</addtitle><date>2019-10-10</date><risdate>2019</risdate><volume>9</volume><issue>1</issue><spage>14618</spage><epage>13</epage><pages>14618-13</pages><artnum>14618</artnum><issn>2045-2322</issn><eissn>2045-2322</eissn><abstract>Memristive switches are able to act as both storage and computing elements, which make them an excellent candidate for beyond-CMOS computing. In this paper, multi-input memristive switch logic is proposed, which enables the function X OR (Y NOR Z) to be performed in a single-step with three memristive switches. This ORNOR logic gate increases the capabilities of memristive switches, improving the overall system efficiency of a memristive switch-based computing architecture. Additionally, a computing system architecture and clocking scheme are proposed to further utilize memristive switching for computation. The system architecture is based on a design where multiple computational function blocks are interconnected and controlled by a master clock that synchronizes system data processing and transfer. The clocking steps to perform a full adder with the ORNOR gate are presented along with simulation results using a physics-based model. The full adder function block is integrated into the system architecture to realize a 64-bit full adder, which is also demonstrated through simulation.</abstract><cop>London</cop><pub>Nature Publishing Group UK</pub><pmid>31602003</pmid><doi>10.1038/s41598-019-51039-6</doi><tpages>13</tpages><orcidid>https://orcid.org/0000-0002-7337-6637</orcidid><orcidid>https://orcid.org/0000-0002-5426-9967</orcidid><orcidid>https://orcid.org/0000-0001-9847-4455</orcidid><orcidid>https://orcid.org/0000-0002-4258-2673</orcidid><oa>free_for_read</oa></addata></record> |
fulltext | fulltext |
identifier | ISSN: 2045-2322 |
ispartof | Scientific reports, 2019-10, Vol.9 (1), p.14618-13, Article 14618 |
issn | 2045-2322 2045-2322 |
language | eng |
recordid | cdi_pubmedcentral_primary_oai_pubmedcentral_nih_gov_6787102 |
source | DOAJ Directory of Open Access Journals; Springer Nature OA Free Journals; Nature Free; EZB-FREE-00999 freely available EZB journals; PubMed Central; Free Full-Text Journals in Chemistry |
subjects | 119/118 639/166/987 639/925/927/1007 Computer applications Data processing Engineering Sciences Humanities and Social Sciences Logic multidisciplinary Science Science (multidisciplinary) Simulation |
title | Stateful Three-Input Logic with Memristive Switches |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-20T11%3A19%3A43IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_pubme&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Stateful%20Three-Input%20Logic%20with%20Memristive%20Switches&rft.jtitle=Scientific%20reports&rft.au=Siemon,%20A.&rft.date=2019-10-10&rft.volume=9&rft.issue=1&rft.spage=14618&rft.epage=13&rft.pages=14618-13&rft.artnum=14618&rft.issn=2045-2322&rft.eissn=2045-2322&rft_id=info:doi/10.1038/s41598-019-51039-6&rft_dat=%3Cproquest_pubme%3E2303724896%3C/proquest_pubme%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=2303724896&rft_id=info:pmid/31602003&rfr_iscdi=true |