Highly scaled (L sub(g [approx] 56 nm) gate-last Si tunnel field-effect transistors with I) sub(O)N 100 mu A/ mu m

Planar band-to-band tunneling FETs (TFETs) have been fabricated on silicon-on-insulator (SOI) substrates using conventional CMOS technologies with a highly scaled sub-60 nm gate length (effective gate length [L sub(g] [approx] 40 nm due to an overlap between the source and gate) and different anneal sequences. The optimal anneal sequence including spike and flash annealing resulted in a drive ON current (I) sub(O)N)) 100 mu A/ mu m with I sub(ON/I) sub(O)FF 10 super(5 at a drain bias of -1 V. The devices exhibited negative differential resistance and non-linear subthreshold temperature dependencies, consistent with the band-to-band tunneling mechanism. Simulations using a 2-D TCAD simulator, MEDICI, agreed with experimental data, demonstrating the possibility of Si tunnel transistors in logic applications.)