A 2.5-V, 333-Mb/s/pin, 1-Gbit, double-data-rate synchronous DRAM
A double data rate (DDR) at 333 Mb/s/pin is achieved for a 2.5-V, 1-Gb synchronous DRAM in a 0.14-/spl mu/m CMOS process. The large density of integration and severe device fluctuation present challenges in dealing with the on-chip skews, packaging, and processing technology. Circuit techniques and...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 1999-11, Vol.34 (11), p.1589-1599 |
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| container_end_page | 1599 |
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| container_issue | 11 |
| container_start_page | 1589 |
| container_title | IEEE journal of solid-state circuits |
| container_volume | 34 |
| creator | Yoon, Hongil Cha, Gi-Won Yoo, Changsik Kim, Nam-Jong Kim, Keum-Yong Lee, Chang Ho Lim, Kyu-Nam Lee, Kyuchan Jeon, Jun-Young Jung, Tae Sung Jeong, Hongsik Chung, Tae-Young Kim, Kinam Cho, Soo In |
| description | A double data rate (DDR) at 333 Mb/s/pin is achieved for a 2.5-V, 1-Gb synchronous DRAM in a 0.14-/spl mu/m CMOS process. The large density of integration and severe device fluctuation present challenges in dealing with the on-chip skews, packaging, and processing technology. Circuit techniques and schemes of outer DQ and inner control (ODIC) chip with a non-ODIC package, cycle-time-adaptive wave pipelining, and variable-stage analog delay-locked loop with the three-input phase detector can provide precise skew controls and increased tolerance to processing variations. DDR as a viable high-speed and low-voltage DRAM I/O interface is demonstrated. |
| doi_str_mv | 10.1109/4.799867 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_proquest_miscellaneous_919922989</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>799867</ieee_id><sourcerecordid>26859559</sourcerecordid><originalsourceid>FETCH-LOGICAL-c338t-1f2bd4f7718cd2b0933f482ce12bd26ac78a066576f78f00091344f97e1e4f903</originalsourceid><addsrcrecordid>eNqF0M9LwzAUB_AgCs4pePbUk-6wbHn50SQ3x9QpbAii4q2kaYKVrp1Jd9h_b0eHRz19ee99eDweQpdAJgBET_lEaq1SeYQGIITCINnHMRoQAgprSsgpOovxqys5VzBAt7OETgR-HyeMMbzKp3G6KetxAniRl-04KZptXjlcmNbgYFqXxF1tP0NTN9uY3L3MVufoxJsquotDDtHbw_3r_BEvnxdP89kSW8ZUi8HTvOBeSlC2oDnRjHmuqHXQ9WlqrFSGpKmQqZfKE0I0MM69lg5cF4QN0U2_dxOa762LbbYuo3VVZWrX3ZJp0JpSrXQnr_-UVAFlUqr_YaqEFmK_cdRDG5oYg_PZJpRrE3YZkGz_9Yxn_dc7etXT0jn3yw7DH_7Qdz8</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>26859559</pqid></control><display><type>article</type><title>A 2.5-V, 333-Mb/s/pin, 1-Gbit, double-data-rate synchronous DRAM</title><source>IEEE Electronic Library (IEL)</source><creator>Yoon, Hongil ; Cha, Gi-Won ; Yoo, Changsik ; Kim, Nam-Jong ; Kim, Keum-Yong ; Lee, Chang Ho ; Lim, Kyu-Nam ; Lee, Kyuchan ; Jeon, Jun-Young ; Jung, Tae Sung ; Jeong, Hongsik ; Chung, Tae-Young ; Kim, Kinam ; Cho, Soo In</creator><creatorcontrib>Yoon, Hongil ; Cha, Gi-Won ; Yoo, Changsik ; Kim, Nam-Jong ; Kim, Keum-Yong ; Lee, Chang Ho ; Lim, Kyu-Nam ; Lee, Kyuchan ; Jeon, Jun-Young ; Jung, Tae Sung ; Jeong, Hongsik ; Chung, Tae-Young ; Kim, Kinam ; Cho, Soo In</creatorcontrib><description>A double data rate (DDR) at 333 Mb/s/pin is achieved for a 2.5-V, 1-Gb synchronous DRAM in a 0.14-/spl mu/m CMOS process. The large density of integration and severe device fluctuation present challenges in dealing with the on-chip skews, packaging, and processing technology. Circuit techniques and schemes of outer DQ and inner control (ODIC) chip with a non-ODIC package, cycle-time-adaptive wave pipelining, and variable-stage analog delay-locked loop with the three-input phase detector can provide precise skew controls and increased tolerance to processing variations. DDR as a viable high-speed and low-voltage DRAM I/O interface is demonstrated.</description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/4.799867</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>IEEE</publisher><subject>Circuits ; CMOS ; CMOS process ; CMOS technology ; Density ; Detectors ; Dynamic random access memory ; Fluctuations ; High speed ; Packages ; Packaging ; Phase detection ; Pipeline processing ; Propagation delay ; Random access memory ; Synchronous ; Tolerances</subject><ispartof>IEEE journal of solid-state circuits, 1999-11, Vol.34 (11), p.1589-1599</ispartof><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c338t-1f2bd4f7718cd2b0933f482ce12bd26ac78a066576f78f00091344f97e1e4f903</citedby><cites>FETCH-LOGICAL-c338t-1f2bd4f7718cd2b0933f482ce12bd26ac78a066576f78f00091344f97e1e4f903</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/799867$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/799867$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Yoon, Hongil</creatorcontrib><creatorcontrib>Cha, Gi-Won</creatorcontrib><creatorcontrib>Yoo, Changsik</creatorcontrib><creatorcontrib>Kim, Nam-Jong</creatorcontrib><creatorcontrib>Kim, Keum-Yong</creatorcontrib><creatorcontrib>Lee, Chang Ho</creatorcontrib><creatorcontrib>Lim, Kyu-Nam</creatorcontrib><creatorcontrib>Lee, Kyuchan</creatorcontrib><creatorcontrib>Jeon, Jun-Young</creatorcontrib><creatorcontrib>Jung, Tae Sung</creatorcontrib><creatorcontrib>Jeong, Hongsik</creatorcontrib><creatorcontrib>Chung, Tae-Young</creatorcontrib><creatorcontrib>Kim, Kinam</creatorcontrib><creatorcontrib>Cho, Soo In</creatorcontrib><title>A 2.5-V, 333-Mb/s/pin, 1-Gbit, double-data-rate synchronous DRAM</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description>A double data rate (DDR) at 333 Mb/s/pin is achieved for a 2.5-V, 1-Gb synchronous DRAM in a 0.14-/spl mu/m CMOS process. The large density of integration and severe device fluctuation present challenges in dealing with the on-chip skews, packaging, and processing technology. Circuit techniques and schemes of outer DQ and inner control (ODIC) chip with a non-ODIC package, cycle-time-adaptive wave pipelining, and variable-stage analog delay-locked loop with the three-input phase detector can provide precise skew controls and increased tolerance to processing variations. DDR as a viable high-speed and low-voltage DRAM I/O interface is demonstrated.</description><subject>Circuits</subject><subject>CMOS</subject><subject>CMOS process</subject><subject>CMOS technology</subject><subject>Density</subject><subject>Detectors</subject><subject>Dynamic random access memory</subject><subject>Fluctuations</subject><subject>High speed</subject><subject>Packages</subject><subject>Packaging</subject><subject>Phase detection</subject><subject>Pipeline processing</subject><subject>Propagation delay</subject><subject>Random access memory</subject><subject>Synchronous</subject><subject>Tolerances</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1999</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNqF0M9LwzAUB_AgCs4pePbUk-6wbHn50SQ3x9QpbAii4q2kaYKVrp1Jd9h_b0eHRz19ee99eDweQpdAJgBET_lEaq1SeYQGIITCINnHMRoQAgprSsgpOovxqys5VzBAt7OETgR-HyeMMbzKp3G6KetxAniRl-04KZptXjlcmNbgYFqXxF1tP0NTN9uY3L3MVufoxJsquotDDtHbw_3r_BEvnxdP89kSW8ZUi8HTvOBeSlC2oDnRjHmuqHXQ9WlqrFSGpKmQqZfKE0I0MM69lg5cF4QN0U2_dxOa762LbbYuo3VVZWrX3ZJp0JpSrXQnr_-UVAFlUqr_YaqEFmK_cdRDG5oYg_PZJpRrE3YZkGz_9Yxn_dc7etXT0jn3yw7DH_7Qdz8</recordid><startdate>19991101</startdate><enddate>19991101</enddate><creator>Yoon, Hongil</creator><creator>Cha, Gi-Won</creator><creator>Yoo, Changsik</creator><creator>Kim, Nam-Jong</creator><creator>Kim, Keum-Yong</creator><creator>Lee, Chang Ho</creator><creator>Lim, Kyu-Nam</creator><creator>Lee, Kyuchan</creator><creator>Jeon, Jun-Young</creator><creator>Jung, Tae Sung</creator><creator>Jeong, Hongsik</creator><creator>Chung, Tae-Young</creator><creator>Kim, Kinam</creator><creator>Cho, Soo In</creator><general>IEEE</general><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SC</scope><scope>7U5</scope><scope>8FD</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope><scope>7SP</scope><scope>F28</scope><scope>FR3</scope><scope>KR7</scope></search><sort><creationdate>19991101</creationdate><title>A 2.5-V, 333-Mb/s/pin, 1-Gbit, double-data-rate synchronous DRAM</title><author>Yoon, Hongil ; Cha, Gi-Won ; Yoo, Changsik ; Kim, Nam-Jong ; Kim, Keum-Yong ; Lee, Chang Ho ; Lim, Kyu-Nam ; Lee, Kyuchan ; Jeon, Jun-Young ; Jung, Tae Sung ; Jeong, Hongsik ; Chung, Tae-Young ; Kim, Kinam ; Cho, Soo In</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c338t-1f2bd4f7718cd2b0933f482ce12bd26ac78a066576f78f00091344f97e1e4f903</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1999</creationdate><topic>Circuits</topic><topic>CMOS</topic><topic>CMOS process</topic><topic>CMOS technology</topic><topic>Density</topic><topic>Detectors</topic><topic>Dynamic random access memory</topic><topic>Fluctuations</topic><topic>High speed</topic><topic>Packages</topic><topic>Packaging</topic><topic>Phase detection</topic><topic>Pipeline processing</topic><topic>Propagation delay</topic><topic>Random access memory</topic><topic>Synchronous</topic><topic>Tolerances</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Yoon, Hongil</creatorcontrib><creatorcontrib>Cha, Gi-Won</creatorcontrib><creatorcontrib>Yoo, Changsik</creatorcontrib><creatorcontrib>Kim, Nam-Jong</creatorcontrib><creatorcontrib>Kim, Keum-Yong</creatorcontrib><creatorcontrib>Lee, Chang Ho</creatorcontrib><creatorcontrib>Lim, Kyu-Nam</creatorcontrib><creatorcontrib>Lee, Kyuchan</creatorcontrib><creatorcontrib>Jeon, Jun-Young</creatorcontrib><creatorcontrib>Jung, Tae Sung</creatorcontrib><creatorcontrib>Jeong, Hongsik</creatorcontrib><creatorcontrib>Chung, Tae-Young</creatorcontrib><creatorcontrib>Kim, Kinam</creatorcontrib><creatorcontrib>Cho, Soo In</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Computer and Information Systems Abstracts</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><collection>Electronics & Communications Abstracts</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><collection>Civil Engineering Abstracts</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Yoon, Hongil</au><au>Cha, Gi-Won</au><au>Yoo, Changsik</au><au>Kim, Nam-Jong</au><au>Kim, Keum-Yong</au><au>Lee, Chang Ho</au><au>Lim, Kyu-Nam</au><au>Lee, Kyuchan</au><au>Jeon, Jun-Young</au><au>Jung, Tae Sung</au><au>Jeong, Hongsik</au><au>Chung, Tae-Young</au><au>Kim, Kinam</au><au>Cho, Soo In</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A 2.5-V, 333-Mb/s/pin, 1-Gbit, double-data-rate synchronous DRAM</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>1999-11-01</date><risdate>1999</risdate><volume>34</volume><issue>11</issue><spage>1589</spage><epage>1599</epage><pages>1589-1599</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract>A double data rate (DDR) at 333 Mb/s/pin is achieved for a 2.5-V, 1-Gb synchronous DRAM in a 0.14-/spl mu/m CMOS process. The large density of integration and severe device fluctuation present challenges in dealing with the on-chip skews, packaging, and processing technology. Circuit techniques and schemes of outer DQ and inner control (ODIC) chip with a non-ODIC package, cycle-time-adaptive wave pipelining, and variable-stage analog delay-locked loop with the three-input phase detector can provide precise skew controls and increased tolerance to processing variations. DDR as a viable high-speed and low-voltage DRAM I/O interface is demonstrated.</abstract><pub>IEEE</pub><doi>10.1109/4.799867</doi><tpages>11</tpages></addata></record> |
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| issn | 0018-9200 1558-173X |
| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Circuits CMOS CMOS process CMOS technology Density Detectors Dynamic random access memory Fluctuations High speed Packages Packaging Phase detection Pipeline processing Propagation delay Random access memory Synchronous Tolerances |
| title | A 2.5-V, 333-Mb/s/pin, 1-Gbit, double-data-rate synchronous DRAM |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-20T08%3A23%3A54IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=A%202.5-V,%20333-Mb/s/pin,%201-Gbit,%20double-data-rate%20synchronous%20DRAM&rft.jtitle=IEEE%20journal%20of%20solid-state%20circuits&rft.au=Yoon,%20Hongil&rft.date=1999-11-01&rft.volume=34&rft.issue=11&rft.spage=1589&rft.epage=1599&rft.pages=1589-1599&rft.issn=0018-9200&rft.eissn=1558-173X&rft.coden=IJSCBC&rft_id=info:doi/10.1109/4.799867&rft_dat=%3Cproquest_RIE%3E26859559%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=26859559&rft_id=info:pmid/&rft_ieee_id=799867&rfr_iscdi=true |