Impact of Hot Carriers on nMOSFET Variability in 45- and 65-nm CMOS Technologies
This paper examines the impact of hot carriers (HCs) on n-channel metal-oxide-semiconductor (MOS) field-effect transistor mismatch across the 45- and 65-nm complementary MOS technology generations. The reported statistical analysis is based on a large overall sample population of about 1000 transist...
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| Veröffentlicht in: | IEEE transactions on electron devices 2011-08, Vol.58 (8), p.2347-2353 |
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| container_title | IEEE transactions on electron devices |
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| creator | Magnone, P. Crupi, F. Wils, N. Jain, R. Tuinhout, H. Andricciola, P. Giusi, G. Fiegna, C. |
| description | This paper examines the impact of hot carriers (HCs) on n-channel metal-oxide-semiconductor (MOS) field-effect transistor mismatch across the 45- and 65-nm complementary MOS technology generations. The reported statistical analysis is based on a large overall sample population of about 1000 transistors. HC stress introduces a source of variability in device electrical parameters due to the randomly generated charge traps in the gate dielectric or at the substrate/dielectric interface. The evolution of the threshold-voltage mismatch during an HC stress is well modeled by assuming a Poisson distribution of the induced charge traps with a nonuniform generation along the channel. Once the evolution of the HC-induced VT shift is known, a single parameter is able to accurately describe the evolution of the HC-induced VT variability. This parameter is independent of the stress time and stress bias voltage. The HC stress causes a significantly larger degradation in the subthreshold slope variability, compared to threshold voltage variability for both investigated technology nodes. |
| doi_str_mv | 10.1109/TED.2011.2156414 |
| format | Article |
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The reported statistical analysis is based on a large overall sample population of about 1000 transistors. HC stress introduces a source of variability in device electrical parameters due to the randomly generated charge traps in the gate dielectric or at the substrate/dielectric interface. The evolution of the threshold-voltage mismatch during an HC stress is well modeled by assuming a Poisson distribution of the induced charge traps with a nonuniform generation along the channel. Once the evolution of the HC-induced VT shift is known, a single parameter is able to accurately describe the evolution of the HC-induced VT variability. This parameter is independent of the stress time and stress bias voltage. The HC stress causes a significantly larger degradation in the subthreshold slope variability, compared to threshold voltage variability for both investigated technology nodes.</description><identifier>ISSN: 0018-9383</identifier><identifier>EISSN: 1557-9646</identifier><identifier>DOI: 10.1109/TED.2011.2156414</identifier><identifier>CODEN: IETDAI</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Carriers ; Charge ; CMOS integrated circuits ; CMOS technology ; Devices ; Electric charge ; Evolution ; Hot carrier (HC) ; Logic gates ; Mathematical models ; metal-oxide-semiconductor field-effect transistor (MOSFET) ; mismatch ; MOSFET circuits ; Semiconductor device modeling ; Statistical analysis ; Stress ; Stresses ; Studies ; subthreshold slope ; threshold voltage ; Transistors ; variability</subject><ispartof>IEEE transactions on electron devices, 2011-08, Vol.58 (8), p.2347-2353</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Aug 2011</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c388t-3d01760c131dc36b53b80924e42722d169327d808880ac7b889f3fc21608b2c73</citedby><cites>FETCH-LOGICAL-c388t-3d01760c131dc36b53b80924e42722d169327d808880ac7b889f3fc21608b2c73</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5934400$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5934400$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Magnone, P.</creatorcontrib><creatorcontrib>Crupi, F.</creatorcontrib><creatorcontrib>Wils, N.</creatorcontrib><creatorcontrib>Jain, R.</creatorcontrib><creatorcontrib>Tuinhout, H.</creatorcontrib><creatorcontrib>Andricciola, P.</creatorcontrib><creatorcontrib>Giusi, G.</creatorcontrib><creatorcontrib>Fiegna, C.</creatorcontrib><title>Impact of Hot Carriers on nMOSFET Variability in 45- and 65-nm CMOS Technologies</title><title>IEEE transactions on electron devices</title><addtitle>TED</addtitle><description>This paper examines the impact of hot carriers (HCs) on n-channel metal-oxide-semiconductor (MOS) field-effect transistor mismatch across the 45- and 65-nm complementary MOS technology generations. The reported statistical analysis is based on a large overall sample population of about 1000 transistors. HC stress introduces a source of variability in device electrical parameters due to the randomly generated charge traps in the gate dielectric or at the substrate/dielectric interface. The evolution of the threshold-voltage mismatch during an HC stress is well modeled by assuming a Poisson distribution of the induced charge traps with a nonuniform generation along the channel. Once the evolution of the HC-induced VT shift is known, a single parameter is able to accurately describe the evolution of the HC-induced VT variability. This parameter is independent of the stress time and stress bias voltage. The HC stress causes a significantly larger degradation in the subthreshold slope variability, compared to threshold voltage variability for both investigated technology nodes.</description><subject>Carriers</subject><subject>Charge</subject><subject>CMOS integrated circuits</subject><subject>CMOS technology</subject><subject>Devices</subject><subject>Electric charge</subject><subject>Evolution</subject><subject>Hot carrier (HC)</subject><subject>Logic gates</subject><subject>Mathematical models</subject><subject>metal-oxide-semiconductor field-effect transistor (MOSFET)</subject><subject>mismatch</subject><subject>MOSFET circuits</subject><subject>Semiconductor device modeling</subject><subject>Statistical analysis</subject><subject>Stress</subject><subject>Stresses</subject><subject>Studies</subject><subject>subthreshold slope</subject><subject>threshold voltage</subject><subject>Transistors</subject><subject>variability</subject><issn>0018-9383</issn><issn>1557-9646</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2011</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpdkEtLAzEURoMoWKt7wU1w42rqzWMyyVLG-oBKBavbkMlkNDKd1GS68N-bUnHh6nLhfPdxEDonMCME1PVqfjujQMiMklJwwg_QhJRlVSjBxSGaABBZKCbZMTpJ6TO3gnM6Qc-P642xIw4dfggjrk2M3sWEw4CHp-XL3XyF30z0pvG9H7-xHzAvC2yGFouyGNa4zhBeOfsxhD68e5dO0VFn-uTOfusUveYh9UOxWN4_1jeLwjIpx4K1QCoBljDSWiaakjUSFOWO04rSlgjFaNVKkFKCsVUjpepYZykRIBtqKzZFV_u5mxi-ti6Neu2TdX1vBhe2SSuiFAXIH0_R5T_yM2zjkI_TslLAGAeVIdhDNoaUouv0Jvq1id-agN4J1lmw3gnWv4Jz5GIf8c65P7xUjPO89wcOtnG5</recordid><startdate>201108</startdate><enddate>201108</enddate><creator>Magnone, P.</creator><creator>Crupi, F.</creator><creator>Wils, N.</creator><creator>Jain, R.</creator><creator>Tuinhout, H.</creator><creator>Andricciola, P.</creator><creator>Giusi, G.</creator><creator>Fiegna, C.</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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The reported statistical analysis is based on a large overall sample population of about 1000 transistors. HC stress introduces a source of variability in device electrical parameters due to the randomly generated charge traps in the gate dielectric or at the substrate/dielectric interface. The evolution of the threshold-voltage mismatch during an HC stress is well modeled by assuming a Poisson distribution of the induced charge traps with a nonuniform generation along the channel. Once the evolution of the HC-induced VT shift is known, a single parameter is able to accurately describe the evolution of the HC-induced VT variability. This parameter is independent of the stress time and stress bias voltage. The HC stress causes a significantly larger degradation in the subthreshold slope variability, compared to threshold voltage variability for both investigated technology nodes.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TED.2011.2156414</doi><tpages>7</tpages></addata></record> |
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| subjects | Carriers Charge CMOS integrated circuits CMOS technology Devices Electric charge Evolution Hot carrier (HC) Logic gates Mathematical models metal-oxide-semiconductor field-effect transistor (MOSFET) mismatch MOSFET circuits Semiconductor device modeling Statistical analysis Stress Stresses Studies subthreshold slope threshold voltage Transistors variability |
| title | Impact of Hot Carriers on nMOSFET Variability in 45- and 65-nm CMOS Technologies |
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