A 1.8∼3.2-GHz fully differential GaAs MESFET PLL

A 1.8-3.2-GHz fully differential phase-locked loop (PLL) is realized for asynchronous transfer mode clock generation applications. The PLL includes a new differential voltage controlled oscillator with the wide tuning range of 1.74 [similar to] 3.40 GHz and a new differential charge pump with improv...

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Veröffentlicht in:	IEEE journal of solid-state circuits 2001-04, Vol.36 (4), p.605-610
Hauptverfasser:	Cheung, Tae-Sik, Lee, Bhum-Cheol, Choi, Eun-Chang, Choi, Woo-Young
Format:	Artikel
Sprache:	eng
Schlagworte:	Asynchronous transfer mode Circuits Clocks Gallium arsenide Gallium arsenides Jitter MESFETs Tuning
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container_end_page	610
container_issue	4
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container_title	IEEE journal of solid-state circuits
container_volume	36
creator	Cheung, Tae-Sik Lee, Bhum-Cheol Choi, Eun-Chang Choi, Woo-Young
description	A 1.8-3.2-GHz fully differential phase-locked loop (PLL) is realized for asynchronous transfer mode clock generation applications. The PLL includes a new differential voltage controlled oscillator with the wide tuning range of 1.74 [similar to] 3.40 GHz and a new differential charge pump with improved hold characteristics. The PLL is implemented with 0.5- mu m GaAs MESFET technology. The experimental results show that the proposed PLL has a lock range of 1.8 [similar to] 3.2 GHz and its output RMS jitter is at most 5.0 ps (0.015 UI) at 3.2 GHz.
doi_str_mv	10.1109/4.913738
format	Article
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The PLL includes a new differential voltage controlled oscillator with the wide tuning range of 1.74 [similar to] 3.40 GHz and a new differential charge pump with improved hold characteristics. The PLL is implemented with 0.5- mu m GaAs MESFET technology. The experimental results show that the proposed PLL has a lock range of 1.8 [similar to] 3.2 GHz and its output RMS jitter is at most 5.0 ps (0.015 UI) at 3.2 GHz.</description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/4.913738</identifier><language>eng</language><publisher>New York: The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</publisher><subject>Asynchronous transfer mode ; Circuits ; Clocks ; Gallium arsenide ; Gallium arsenides ; Jitter ; MESFETs ; Tuning</subject><ispartof>IEEE journal of solid-state circuits, 2001-04, Vol.36 (4), p.605-610</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. 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The experimental results show that the proposed PLL has a lock range of 1.8 [similar to] 3.2 GHz and its output RMS jitter is at most 5.0 ps (0.015 UI) at 3.2 GHz.</description><subject>Asynchronous transfer mode</subject><subject>Circuits</subject><subject>Clocks</subject><subject>Gallium arsenide</subject><subject>Gallium arsenides</subject><subject>Jitter</subject><subject>MESFETs</subject><subject>Tuning</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2001</creationdate><recordtype>article</recordtype><recordid>eNqF0cFKw0AQBuBFFKxV8BGCB_WSuLM72eweS6mpEFFQwduym-xCStrUbHOoT-BD-TQ-iSn15EFPwzAfwww_IedAEwCqbjBRwDMuD8gI0lTGkPHXQzKiFGSsGKXH5CSExdAiShgRNokgkV8fnzxhcT5_j3zfNNuoqr13nVttatNEuZmE6H72dDt7jh6L4pQcedMEd_ZTx-RlmEzncfGQ300nRVwyAZtYeMGr4aKMGoOlFWCZt8pwK0rKQFZMcGpdZhgqaW2VIXqfKkRqKRMSOR-Tq_3edde-9S5s9LIOpWsas3JtH7QCFIKhgEFe_imZBMUkpv9DASJLOR3gxS-4aPtuNbyrlRIpYCp3B17vUdm1IXTO63VXL0231UD1LgyNeh8G_wZtV3Z_</recordid><startdate>20010401</startdate><enddate>20010401</enddate><creator>Cheung, Tae-Sik</creator><creator>Lee, Bhum-Cheol</creator><creator>Choi, Eun-Chang</creator><creator>Choi, Woo-Young</creator><general>The Institute of Electrical and Electronics Engineers, Inc. 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source	IEEE Electronic Library (IEL)
subjects	Asynchronous transfer mode Circuits Clocks Gallium arsenide Gallium arsenides Jitter MESFETs Tuning
title	A 1.8∼3.2-GHz fully differential GaAs MESFET PLL
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