Novel materials for thermal via incorporation into SOI structures

Self-heating effects in ICs on silicon-on-insulator (SOI) substrates are due to the thick buried oxide layer present in the SOI substrate. Silicon dioxide has a poor thermal conductivity value (0.4-1.2WK^sup -1^m^sup -1^), compared with silicon (150WK^sup -1^m^sup -1^). In order to minimize this sel...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:Journal of materials science. Materials in electronics 2001-06, Vol.12 (4-6), p.215-218
Hauptverfasser: Baine, P, Choon, Khor Yeap, Gamble, H S, Armstrong, B M, Mitchell, S J, N
Format: Artikel
Sprache:eng
Schlagworte:
Online-Zugang:Volltext
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page 218
container_issue 4-6
container_start_page 215
container_title Journal of materials science. Materials in electronics
container_volume 12
creator Baine, P
Choon, Khor Yeap
Gamble, H S
Armstrong, B M
Mitchell, S J
N
description Self-heating effects in ICs on silicon-on-insulator (SOI) substrates are due to the thick buried oxide layer present in the SOI substrate. Silicon dioxide has a poor thermal conductivity value (0.4-1.2WK^sup -1^m^sup -1^), compared with silicon (150WK^sup -1^m^sup -1^). In order to minimize this self-heating, the use of multiple-layer structures as thermal vias (TV) is investigated. The vias have been fabricated as sandwich layers with thin SiO^sub 2^ (20 nm) enclosing low pressure chemical vapor deposited (LPCVD) silicon layers (1 βm), all IC compatible materials. The LPCVD silicon layers consisted of either polycrystalline silicon or a combination of amorphous silicon and polysilicon. Electrical testing of the oxide/silicon structures has shown that inclusion of an amorphous silicon layer in the oxide sandwich improves the interface between the oxide and the silicon layer. This provides better electrical stability with an operational capability >30 V. The capacitance of the multi-layer structure (96 pF), as measured at frequencies ≥1 MHz, confirms that the polysilicon behaves as a dielectric layer at these frequencies. Thermal conductivity assessment, using a four-terminal resistor structure, shows that the multilayer via offers an improved thermal conductivity (3.5WK^sup -1^m^sup -1^0 when compared to a 1-βm homogenous buried oxide layer (0.8WK^sup -1^m^sup -1^)[PUBLICATION ABSTRACT]
doi_str_mv 10.1023/A:1011247000996
format Article
fullrecord <record><control><sourceid>proquest</sourceid><recordid>TN_cdi_proquest_miscellaneous_914649395</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>2419922471</sourcerecordid><originalsourceid>FETCH-LOGICAL-p212t-eaf2f0492e5c3ed3d0d4c39b832129e1324a6b88025473a8e1f55b823e169c343</originalsourceid><addsrcrecordid>eNpdjk1LxDAYhIMoWFfPXoMXT9Ukb9Im3srix8LiHlTwVtL0LXbpNjVJ9_db0JOnYZhnhiHkmrM7zgTcVw-ccS5kyRgzpjghGVcl5FKLz1OSMaPKXCohzslFjPuFKSTojFSv_ogDPdiEobdDpJ0PNH1hONiBHntL-9H5MPlgU-_HxSVP33YbGlOYXZoDxkty1i1FvPrTFfl4enxfv-Tb3fNmXW3zSXCRcrSd6Jg0ApUDbKFlrXRgGg1LbJCDkLZotGZCyRKsRt4p1WgByAvjQMKK3P7uTsF_zxhTfeijw2GwI_o51obLQhowaiFv_pF7P4dxOVdrzQulpGLwA4adWJc</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>881655450</pqid></control><display><type>article</type><title>Novel materials for thermal via incorporation into SOI structures</title><source>Springer Nature - Complete Springer Journals</source><creator>Baine, P ; Choon, Khor Yeap ; Gamble, H S ; Armstrong, B M ; Mitchell, S J; N</creator><creatorcontrib>Baine, P ; Choon, Khor Yeap ; Gamble, H S ; Armstrong, B M ; Mitchell, S J; N</creatorcontrib><description>Self-heating effects in ICs on silicon-on-insulator (SOI) substrates are due to the thick buried oxide layer present in the SOI substrate. Silicon dioxide has a poor thermal conductivity value (0.4-1.2WK^sup -1^m^sup -1^), compared with silicon (150WK^sup -1^m^sup -1^). In order to minimize this self-heating, the use of multiple-layer structures as thermal vias (TV) is investigated. The vias have been fabricated as sandwich layers with thin SiO^sub 2^ (20 nm) enclosing low pressure chemical vapor deposited (LPCVD) silicon layers (1 βm), all IC compatible materials. The LPCVD silicon layers consisted of either polycrystalline silicon or a combination of amorphous silicon and polysilicon. Electrical testing of the oxide/silicon structures has shown that inclusion of an amorphous silicon layer in the oxide sandwich improves the interface between the oxide and the silicon layer. This provides better electrical stability with an operational capability &gt;30 V. The capacitance of the multi-layer structure (96 pF), as measured at frequencies ≥1 MHz, confirms that the polysilicon behaves as a dielectric layer at these frequencies. Thermal conductivity assessment, using a four-terminal resistor structure, shows that the multilayer via offers an improved thermal conductivity (3.5WK^sup -1^m^sup -1^0 when compared to a 1-βm homogenous buried oxide layer (0.8WK^sup -1^m^sup -1^)[PUBLICATION ABSTRACT]</description><identifier>ISSN: 0957-4522</identifier><identifier>EISSN: 1573-482X</identifier><identifier>DOI: 10.1023/A:1011247000996</identifier><language>eng</language><publisher>New York: Springer Nature B.V</publisher><subject>Amorphous silicon ; Electronics ; Heat transfer ; Multilayers ; Oxides ; Silicon ; Silicon dioxide ; Solar energy ; Thermal conductivity</subject><ispartof>Journal of materials science. Materials in electronics, 2001-06, Vol.12 (4-6), p.215-218</ispartof><rights>Kluwer Academic Publishers 2001</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><link.rule.ids>314,776,780,27901,27902</link.rule.ids></links><search><creatorcontrib>Baine, P</creatorcontrib><creatorcontrib>Choon, Khor Yeap</creatorcontrib><creatorcontrib>Gamble, H S</creatorcontrib><creatorcontrib>Armstrong, B M</creatorcontrib><creatorcontrib>Mitchell, S J; N</creatorcontrib><title>Novel materials for thermal via incorporation into SOI structures</title><title>Journal of materials science. Materials in electronics</title><description>Self-heating effects in ICs on silicon-on-insulator (SOI) substrates are due to the thick buried oxide layer present in the SOI substrate. Silicon dioxide has a poor thermal conductivity value (0.4-1.2WK^sup -1^m^sup -1^), compared with silicon (150WK^sup -1^m^sup -1^). In order to minimize this self-heating, the use of multiple-layer structures as thermal vias (TV) is investigated. The vias have been fabricated as sandwich layers with thin SiO^sub 2^ (20 nm) enclosing low pressure chemical vapor deposited (LPCVD) silicon layers (1 βm), all IC compatible materials. The LPCVD silicon layers consisted of either polycrystalline silicon or a combination of amorphous silicon and polysilicon. Electrical testing of the oxide/silicon structures has shown that inclusion of an amorphous silicon layer in the oxide sandwich improves the interface between the oxide and the silicon layer. This provides better electrical stability with an operational capability &gt;30 V. The capacitance of the multi-layer structure (96 pF), as measured at frequencies ≥1 MHz, confirms that the polysilicon behaves as a dielectric layer at these frequencies. Thermal conductivity assessment, using a four-terminal resistor structure, shows that the multilayer via offers an improved thermal conductivity (3.5WK^sup -1^m^sup -1^0 when compared to a 1-βm homogenous buried oxide layer (0.8WK^sup -1^m^sup -1^)[PUBLICATION ABSTRACT]</description><subject>Amorphous silicon</subject><subject>Electronics</subject><subject>Heat transfer</subject><subject>Multilayers</subject><subject>Oxides</subject><subject>Silicon</subject><subject>Silicon dioxide</subject><subject>Solar energy</subject><subject>Thermal conductivity</subject><issn>0957-4522</issn><issn>1573-482X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2001</creationdate><recordtype>article</recordtype><sourceid>BENPR</sourceid><recordid>eNpdjk1LxDAYhIMoWFfPXoMXT9Ukb9Im3srix8LiHlTwVtL0LXbpNjVJ9_db0JOnYZhnhiHkmrM7zgTcVw-ccS5kyRgzpjghGVcl5FKLz1OSMaPKXCohzslFjPuFKSTojFSv_ogDPdiEobdDpJ0PNH1hONiBHntL-9H5MPlgU-_HxSVP33YbGlOYXZoDxkty1i1FvPrTFfl4enxfv-Tb3fNmXW3zSXCRcrSd6Jg0ApUDbKFlrXRgGg1LbJCDkLZotGZCyRKsRt4p1WgByAvjQMKK3P7uTsF_zxhTfeijw2GwI_o51obLQhowaiFv_pF7P4dxOVdrzQulpGLwA4adWJc</recordid><startdate>20010601</startdate><enddate>20010601</enddate><creator>Baine, P</creator><creator>Choon, Khor Yeap</creator><creator>Gamble, H S</creator><creator>Armstrong, B M</creator><creator>Mitchell, S J; N</creator><general>Springer Nature B.V</general><scope>7SP</scope><scope>7SR</scope><scope>8BQ</scope><scope>8FD</scope><scope>8FE</scope><scope>8FG</scope><scope>ABJCF</scope><scope>AFKRA</scope><scope>ARAPS</scope><scope>BENPR</scope><scope>BGLVJ</scope><scope>CCPQU</scope><scope>D1I</scope><scope>DWQXO</scope><scope>F28</scope><scope>FR3</scope><scope>HCIFZ</scope><scope>JG9</scope><scope>KB.</scope><scope>L7M</scope><scope>P5Z</scope><scope>P62</scope><scope>PDBOC</scope><scope>PQEST</scope><scope>PQQKQ</scope><scope>PQUKI</scope><scope>S0W</scope></search><sort><creationdate>20010601</creationdate><title>Novel materials for thermal via incorporation into SOI structures</title><author>Baine, P ; Choon, Khor Yeap ; Gamble, H S ; Armstrong, B M ; Mitchell, S J; N</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-p212t-eaf2f0492e5c3ed3d0d4c39b832129e1324a6b88025473a8e1f55b823e169c343</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2001</creationdate><topic>Amorphous silicon</topic><topic>Electronics</topic><topic>Heat transfer</topic><topic>Multilayers</topic><topic>Oxides</topic><topic>Silicon</topic><topic>Silicon dioxide</topic><topic>Solar energy</topic><topic>Thermal conductivity</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Baine, P</creatorcontrib><creatorcontrib>Choon, Khor Yeap</creatorcontrib><creatorcontrib>Gamble, H S</creatorcontrib><creatorcontrib>Armstrong, B M</creatorcontrib><creatorcontrib>Mitchell, S J; N</creatorcontrib><collection>Electronics &amp; Communications Abstracts</collection><collection>Engineered Materials Abstracts</collection><collection>METADEX</collection><collection>Technology Research Database</collection><collection>ProQuest SciTech Collection</collection><collection>ProQuest Technology Collection</collection><collection>Materials Science &amp; Engineering Collection</collection><collection>ProQuest Central UK/Ireland</collection><collection>Advanced Technologies &amp; Aerospace Collection</collection><collection>ProQuest Central</collection><collection>Technology Collection</collection><collection>ProQuest One Community College</collection><collection>ProQuest Materials Science Collection</collection><collection>ProQuest Central Korea</collection><collection>ANTE: Abstracts in New Technology &amp; Engineering</collection><collection>Engineering Research Database</collection><collection>SciTech Premium Collection</collection><collection>Materials Research Database</collection><collection>Materials Science Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Advanced Technologies &amp; Aerospace Database</collection><collection>ProQuest Advanced Technologies &amp; Aerospace Collection</collection><collection>Materials Science Collection</collection><collection>ProQuest One Academic Eastern Edition (DO NOT USE)</collection><collection>ProQuest One Academic</collection><collection>ProQuest One Academic UKI Edition</collection><collection>DELNET Engineering &amp; Technology Collection</collection><jtitle>Journal of materials science. Materials in electronics</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Baine, P</au><au>Choon, Khor Yeap</au><au>Gamble, H S</au><au>Armstrong, B M</au><au>Mitchell, S J; N</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Novel materials for thermal via incorporation into SOI structures</atitle><jtitle>Journal of materials science. Materials in electronics</jtitle><date>2001-06-01</date><risdate>2001</risdate><volume>12</volume><issue>4-6</issue><spage>215</spage><epage>218</epage><pages>215-218</pages><issn>0957-4522</issn><eissn>1573-482X</eissn><abstract>Self-heating effects in ICs on silicon-on-insulator (SOI) substrates are due to the thick buried oxide layer present in the SOI substrate. Silicon dioxide has a poor thermal conductivity value (0.4-1.2WK^sup -1^m^sup -1^), compared with silicon (150WK^sup -1^m^sup -1^). In order to minimize this self-heating, the use of multiple-layer structures as thermal vias (TV) is investigated. The vias have been fabricated as sandwich layers with thin SiO^sub 2^ (20 nm) enclosing low pressure chemical vapor deposited (LPCVD) silicon layers (1 βm), all IC compatible materials. The LPCVD silicon layers consisted of either polycrystalline silicon or a combination of amorphous silicon and polysilicon. Electrical testing of the oxide/silicon structures has shown that inclusion of an amorphous silicon layer in the oxide sandwich improves the interface between the oxide and the silicon layer. This provides better electrical stability with an operational capability &gt;30 V. The capacitance of the multi-layer structure (96 pF), as measured at frequencies ≥1 MHz, confirms that the polysilicon behaves as a dielectric layer at these frequencies. Thermal conductivity assessment, using a four-terminal resistor structure, shows that the multilayer via offers an improved thermal conductivity (3.5WK^sup -1^m^sup -1^0 when compared to a 1-βm homogenous buried oxide layer (0.8WK^sup -1^m^sup -1^)[PUBLICATION ABSTRACT]</abstract><cop>New York</cop><pub>Springer Nature B.V</pub><doi>10.1023/A:1011247000996</doi><tpages>4</tpages></addata></record>
fulltext fulltext
identifier ISSN: 0957-4522
ispartof Journal of materials science. Materials in electronics, 2001-06, Vol.12 (4-6), p.215-218
issn 0957-4522
1573-482X
language eng
recordid cdi_proquest_miscellaneous_914649395
source Springer Nature - Complete Springer Journals
subjects Amorphous silicon
Electronics
Heat transfer
Multilayers
Oxides
Silicon
Silicon dioxide
Solar energy
Thermal conductivity
title Novel materials for thermal via incorporation into SOI structures
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-30T22%3A07%3A57IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Novel%20materials%20for%20thermal%20via%20incorporation%20into%20SOI%20structures&rft.jtitle=Journal%20of%20materials%20science.%20Materials%20in%20electronics&rft.au=Baine,%20P&rft.date=2001-06-01&rft.volume=12&rft.issue=4-6&rft.spage=215&rft.epage=218&rft.pages=215-218&rft.issn=0957-4522&rft.eissn=1573-482X&rft_id=info:doi/10.1023/A:1011247000996&rft_dat=%3Cproquest%3E2419922471%3C/proquest%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=881655450&rft_id=info:pmid/&rfr_iscdi=true