A closed-form back-gate-bias related inverse narrow-channel effect model for deep-submicron VLSI CMOS devices using shallow trench isolation

This paper reports an analytical inverse narrow-channel effect threshold voltage model for shallow-trench-isolated (STI) CMOS devices using a conformal mapping technique to simplify the two-dimensional (2-D) analysis. As verified by the experimentally measured data and the 2-D simulation results, th...

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Veröffentlicht in:	IEEE transactions on electron devices 2000-04, Vol.47 (4), p.725-733
Hauptverfasser:	Shih-Chia Lin, Kuo, J.B., Kuo-Tai Huang, Shih-Wei Sun
Format:	Artikel
Sprache:	eng
Schlagworte:	CMOS Conductance Devices Exact solutions Inverse Isolation technology Mathematical analysis Mathematical models Threshold voltage
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