An ultra-fast instruction set simulator

In this paper, we present new techniques which further improve the static compilation-based instruction set architecture (ISA) simulation by the aggressive utilization of the host machine resources. Such utilization is achieved by defining a low-level code-generation interface specialized for ISA si...

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Veröffentlicht in:	IEEE transactions on very large scale integration (VLSI) systems 2002-06, Vol.10 (3), p.363-373
Hauptverfasser:	Jianwen Zhu, Gajski, D.D.
Format:	Artikel
Sprache:	eng
Schlagworte:	Application software Applied sciences Architecture Computational modeling Computer aided instruction Computer simulation Computers, microcomputers Electronics Exact sciences and technology Hardware Instruction sets Integrated circuits Integrated circuits by function (including memories and processors) Logic Process design Registers Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Simulation Utilization Very large scale integration Workstations
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