A 2.5-Mb/s GFSK 5.0-Mb/s 4-FSK automatically calibrated capital sigma - Delta frequency synthesizer
This paper describes a new sigma-delta ( capital sigma - Delta ) frequency synthesizer for Gaussian frequency and minimum shift keying (GFSK/GMSK) modulation. The key innovation is an automatic calibration circuit which tunes the phase-locked loop (PLL) response to compensate for process tolerance a...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 2002-01, Vol.37 (1), p.18-26 |
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| container_title | IEEE journal of solid-state circuits |
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| creator | McMahill, Daniel R Sodini, Charles G |
| description | This paper describes a new sigma-delta ( capital sigma - Delta ) frequency synthesizer for Gaussian frequency and minimum shift keying (GFSK/GMSK) modulation. The key innovation is an automatic calibration circuit which tunes the phase-locked loop (PLL) response to compensate for process tolerance and temperature variation. The availability of this new calibration method allows the use of precompensation techniques to achieve high data rate modulation without requiring factory calibration. The calibration method can be applied to GFSK /GMSK modulation and also M-ary FSK modulation. The PLL, including 1.8-GHz voltage controlled oscillator (VCO), capital sigma - Delta modulator, and automatic calibration circuit, has been implemented in a 0.6- mu m BiCMOS integrated circuit. The test chip achieves 2.5 Mb/s using GFSK and 5.0 Mb/s using 4-FSK. |
| doi_str_mv | 10.1109/4.974542 |
| format | Article |
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The key innovation is an automatic calibration circuit which tunes the phase-locked loop (PLL) response to compensate for process tolerance and temperature variation. The availability of this new calibration method allows the use of precompensation techniques to achieve high data rate modulation without requiring factory calibration. The calibration method can be applied to GFSK /GMSK modulation and also M-ary FSK modulation. The PLL, including 1.8-GHz voltage controlled oscillator (VCO), capital sigma - Delta modulator, and automatic calibration circuit, has been implemented in a 0.6- mu m BiCMOS integrated circuit. The test chip achieves 2.5 Mb/s using GFSK and 5.0 Mb/s using 4-FSK.</description><identifier>ISSN: 0018-9200</identifier><identifier>DOI: 10.1109/4.974542</identifier><language>eng</language><subject>Availability ; Calibration ; Circuits ; Gaussian ; Industrial engineering ; Modulation ; Plants ; Tolerances</subject><ispartof>IEEE journal of solid-state circuits, 2002-01, Vol.37 (1), p.18-26</ispartof><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><link.rule.ids>314,780,784,27924,27925</link.rule.ids></links><search><creatorcontrib>McMahill, Daniel R</creatorcontrib><creatorcontrib>Sodini, Charles G</creatorcontrib><title>A 2.5-Mb/s GFSK 5.0-Mb/s 4-FSK automatically calibrated capital sigma - Delta frequency synthesizer</title><title>IEEE journal of solid-state circuits</title><description>This paper describes a new sigma-delta ( capital sigma - Delta ) frequency synthesizer for Gaussian frequency and minimum shift keying (GFSK/GMSK) modulation. The key innovation is an automatic calibration circuit which tunes the phase-locked loop (PLL) response to compensate for process tolerance and temperature variation. The availability of this new calibration method allows the use of precompensation techniques to achieve high data rate modulation without requiring factory calibration. The calibration method can be applied to GFSK /GMSK modulation and also M-ary FSK modulation. The PLL, including 1.8-GHz voltage controlled oscillator (VCO), capital sigma - Delta modulator, and automatic calibration circuit, has been implemented in a 0.6- mu m BiCMOS integrated circuit. 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The key innovation is an automatic calibration circuit which tunes the phase-locked loop (PLL) response to compensate for process tolerance and temperature variation. The availability of this new calibration method allows the use of precompensation techniques to achieve high data rate modulation without requiring factory calibration. The calibration method can be applied to GFSK /GMSK modulation and also M-ary FSK modulation. The PLL, including 1.8-GHz voltage controlled oscillator (VCO), capital sigma - Delta modulator, and automatic calibration circuit, has been implemented in a 0.6- mu m BiCMOS integrated circuit. The test chip achieves 2.5 Mb/s using GFSK and 5.0 Mb/s using 4-FSK.</abstract><doi>10.1109/4.974542</doi><tpages>9</tpages></addata></record> |
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| ispartof | IEEE journal of solid-state circuits, 2002-01, Vol.37 (1), p.18-26 |
| issn | 0018-9200 |
| language | eng |
| recordid | cdi_proquest_miscellaneous_907965763 |
| source | IEEE Electronic Library (IEL) |
| subjects | Availability Calibration Circuits Gaussian Industrial engineering Modulation Plants Tolerances |
| title | A 2.5-Mb/s GFSK 5.0-Mb/s 4-FSK automatically calibrated capital sigma - Delta frequency synthesizer |
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