Modeling and analysis of 96.5Sn-3.5Ag lead-free solder joints of wafer level chip scale package on buildup microvia printed circuit board
In this study, time-temperature-dependent nonlinear analyses of lead-free solder bumped wafer level chip scale package (WLCSP) on microvia buildup printed circuit board (PCB) assemblies subjected to thermal cycling conditions are presented. The lead-free solder considered is 96.5Sn-3.5Ag. The 62Sn-2...
Gespeichert in:
| Veröffentlicht in: | IEEE transactions on electronics packaging manufacturing 2002-01, Vol.25 (1), p.51-58 |
|---|---|
| Hauptverfasser: | , |
| Format: | Artikel |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 58 |
|---|---|
| container_issue | 1 |
| container_start_page | 51 |
| container_title | IEEE transactions on electronics packaging manufacturing |
| container_volume | 25 |
| creator | Lau, J.H. Lee, S.-W.R. |
| description | In this study, time-temperature-dependent nonlinear analyses of lead-free solder bumped wafer level chip scale package (WLCSP) on microvia buildup printed circuit board (PCB) assemblies subjected to thermal cycling conditions are presented. The lead-free solder considered is 96.5Sn-3.5Ag. The 62Sn-2Ag-36Pb solder is also considered to establish a baseline. These two solder alloys are assumed to obey the Garofalo-Arrhenius steady-state creep constitutive law. The shear stress and shear creep strain hysteresis loops, shear stress history, shear creep strain history, and creep strain density range at the corner solder joint are presented for a better understanding of the thermal-mechanical behavior of the lead-free solder bumped WLCSP on microvia buildup PCB assemblies. |
| doi_str_mv | 10.1109/TEPM.2002.1000483 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_proquest_miscellaneous_907964981</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>1000483</ieee_id><sourcerecordid>28356168</sourcerecordid><originalsourceid>FETCH-LOGICAL-c360t-e55455de23730d351572af16d4591b3fae00286e3464e5817755a2dfd57e86ae3</originalsourceid><addsrcrecordid>eNqNkl9rFDEUxQdRsFY_gPgSBOvTjPl3M5nHUqoWWhSs4FvITu6sWbOTMdmp9CP4rc10Fyo-qA8hCfzO4XLuqarnjDaM0e7N9fnHq4ZTyhtGKZVaPKiOGICuqeb84fLmrBZCfnlcPcl5QymTwPlR9fMqOgx-XBM7unJsuM0-kziQTjXwaaxFA6drEtC6ekiIJMfgMJFN9OPujvthh_IPeIOB9F_9RHJvA5LJ9t_sGkkcyWr2wc0T2fo-xRtvyZSKGB3pfepnvyOraJN7Wj0abMj47HAfV5_fnl-fva8vP7y7ODu9rHuh6K5GAAngkItWUCeAQcvtwJST0LGVGCyWELRCIZVE0KxtASx3g4MWtbIojqvXe98pxe8z5p3Z-txjCHbEOGfT0bZTstOskCd_JXknoNWa_hvU7d24_wEKUEzpAr78A9zEOZXtZKO1lIIrxgvE9lCJNeeEgynBbm26NYyapRVmaYVZWmEOrSiaVwdju-xpSHbsfb4XCgW86xbuxZ7ziPib797lF26Wvis</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>884432612</pqid></control><display><type>article</type><title>Modeling and analysis of 96.5Sn-3.5Ag lead-free solder joints of wafer level chip scale package on buildup microvia printed circuit board</title><source>IEEE Electronic Library (IEL)</source><creator>Lau, J.H. ; Lee, S.-W.R.</creator><creatorcontrib>Lau, J.H. ; Lee, S.-W.R.</creatorcontrib><description>In this study, time-temperature-dependent nonlinear analyses of lead-free solder bumped wafer level chip scale package (WLCSP) on microvia buildup printed circuit board (PCB) assemblies subjected to thermal cycling conditions are presented. The lead-free solder considered is 96.5Sn-3.5Ag. The 62Sn-2Ag-36Pb solder is also considered to establish a baseline. These two solder alloys are assumed to obey the Garofalo-Arrhenius steady-state creep constitutive law. The shear stress and shear creep strain hysteresis loops, shear stress history, shear creep strain history, and creep strain density range at the corner solder joint are presented for a better understanding of the thermal-mechanical behavior of the lead-free solder bumped WLCSP on microvia buildup PCB assemblies.</description><identifier>ISSN: 1521-334X</identifier><identifier>EISSN: 1558-0822</identifier><identifier>DOI: 10.1109/TEPM.2002.1000483</identifier><identifier>CODEN: ITEPFL</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Assembly ; Capacitive sensors ; Chip scale packaging ; Chips ; Circuit boards ; Construction ; Creep ; Creep (materials) ; Electronic equipment and fabrication. Passive components, printed wiring boards, connectics ; Electronics ; Environmentally friendly manufacturing techniques ; Exact sciences and technology ; History ; Lead ; Packages ; Printed circuits ; Semiconductor device modeling ; Soldering ; Solders ; Strain ; Testing, measurement, noise and reliability ; Thermal stresses ; Tin base alloys</subject><ispartof>IEEE transactions on electronics packaging manufacturing, 2002-01, Vol.25 (1), p.51-58</ispartof><rights>2002 INIST-CNRS</rights><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2002</rights><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c360t-e55455de23730d351572af16d4591b3fae00286e3464e5817755a2dfd57e86ae3</citedby><cites>FETCH-LOGICAL-c360t-e55455de23730d351572af16d4591b3fae00286e3464e5817755a2dfd57e86ae3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1000483$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,4022,27922,27923,27924,54757</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1000483$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=13652993$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Lau, J.H.</creatorcontrib><creatorcontrib>Lee, S.-W.R.</creatorcontrib><title>Modeling and analysis of 96.5Sn-3.5Ag lead-free solder joints of wafer level chip scale package on buildup microvia printed circuit board</title><title>IEEE transactions on electronics packaging manufacturing</title><addtitle>TEPM</addtitle><description>In this study, time-temperature-dependent nonlinear analyses of lead-free solder bumped wafer level chip scale package (WLCSP) on microvia buildup printed circuit board (PCB) assemblies subjected to thermal cycling conditions are presented. The lead-free solder considered is 96.5Sn-3.5Ag. The 62Sn-2Ag-36Pb solder is also considered to establish a baseline. These two solder alloys are assumed to obey the Garofalo-Arrhenius steady-state creep constitutive law. The shear stress and shear creep strain hysteresis loops, shear stress history, shear creep strain history, and creep strain density range at the corner solder joint are presented for a better understanding of the thermal-mechanical behavior of the lead-free solder bumped WLCSP on microvia buildup PCB assemblies.</description><subject>Applied sciences</subject><subject>Assembly</subject><subject>Capacitive sensors</subject><subject>Chip scale packaging</subject><subject>Chips</subject><subject>Circuit boards</subject><subject>Construction</subject><subject>Creep</subject><subject>Creep (materials)</subject><subject>Electronic equipment and fabrication. Passive components, printed wiring boards, connectics</subject><subject>Electronics</subject><subject>Environmentally friendly manufacturing techniques</subject><subject>Exact sciences and technology</subject><subject>History</subject><subject>Lead</subject><subject>Packages</subject><subject>Printed circuits</subject><subject>Semiconductor device modeling</subject><subject>Soldering</subject><subject>Solders</subject><subject>Strain</subject><subject>Testing, measurement, noise and reliability</subject><subject>Thermal stresses</subject><subject>Tin base alloys</subject><issn>1521-334X</issn><issn>1558-0822</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2002</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNqNkl9rFDEUxQdRsFY_gPgSBOvTjPl3M5nHUqoWWhSs4FvITu6sWbOTMdmp9CP4rc10Fyo-qA8hCfzO4XLuqarnjDaM0e7N9fnHq4ZTyhtGKZVaPKiOGICuqeb84fLmrBZCfnlcPcl5QymTwPlR9fMqOgx-XBM7unJsuM0-kziQTjXwaaxFA6drEtC6ekiIJMfgMJFN9OPujvthh_IPeIOB9F_9RHJvA5LJ9t_sGkkcyWr2wc0T2fo-xRtvyZSKGB3pfepnvyOraJN7Wj0abMj47HAfV5_fnl-fva8vP7y7ODu9rHuh6K5GAAngkItWUCeAQcvtwJST0LGVGCyWELRCIZVE0KxtASx3g4MWtbIojqvXe98pxe8z5p3Z-txjCHbEOGfT0bZTstOskCd_JXknoNWa_hvU7d24_wEKUEzpAr78A9zEOZXtZKO1lIIrxgvE9lCJNeeEgynBbm26NYyapRVmaYVZWmEOrSiaVwdju-xpSHbsfb4XCgW86xbuxZ7ziPib797lF26Wvis</recordid><startdate>200201</startdate><enddate>200201</enddate><creator>Lau, J.H.</creator><creator>Lee, S.-W.R.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>RIA</scope><scope>RIE</scope><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>8BQ</scope><scope>JG9</scope><scope>7TB</scope><scope>FR3</scope><scope>F28</scope></search><sort><creationdate>200201</creationdate><title>Modeling and analysis of 96.5Sn-3.5Ag lead-free solder joints of wafer level chip scale package on buildup microvia printed circuit board</title><author>Lau, J.H. ; Lee, S.-W.R.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c360t-e55455de23730d351572af16d4591b3fae00286e3464e5817755a2dfd57e86ae3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2002</creationdate><topic>Applied sciences</topic><topic>Assembly</topic><topic>Capacitive sensors</topic><topic>Chip scale packaging</topic><topic>Chips</topic><topic>Circuit boards</topic><topic>Construction</topic><topic>Creep</topic><topic>Creep (materials)</topic><topic>Electronic equipment and fabrication. Passive components, printed wiring boards, connectics</topic><topic>Electronics</topic><topic>Environmentally friendly manufacturing techniques</topic><topic>Exact sciences and technology</topic><topic>History</topic><topic>Lead</topic><topic>Packages</topic><topic>Printed circuits</topic><topic>Semiconductor device modeling</topic><topic>Soldering</topic><topic>Solders</topic><topic>Strain</topic><topic>Testing, measurement, noise and reliability</topic><topic>Thermal stresses</topic><topic>Tin base alloys</topic><toplevel>online_resources</toplevel><creatorcontrib>Lau, J.H.</creatorcontrib><creatorcontrib>Lee, S.-W.R.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>METADEX</collection><collection>Materials Research Database</collection><collection>Mechanical & Transportation Engineering Abstracts</collection><collection>Engineering Research Database</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><jtitle>IEEE transactions on electronics packaging manufacturing</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Lau, J.H.</au><au>Lee, S.-W.R.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Modeling and analysis of 96.5Sn-3.5Ag lead-free solder joints of wafer level chip scale package on buildup microvia printed circuit board</atitle><jtitle>IEEE transactions on electronics packaging manufacturing</jtitle><stitle>TEPM</stitle><date>2002-01</date><risdate>2002</risdate><volume>25</volume><issue>1</issue><spage>51</spage><epage>58</epage><pages>51-58</pages><issn>1521-334X</issn><eissn>1558-0822</eissn><coden>ITEPFL</coden><abstract>In this study, time-temperature-dependent nonlinear analyses of lead-free solder bumped wafer level chip scale package (WLCSP) on microvia buildup printed circuit board (PCB) assemblies subjected to thermal cycling conditions are presented. The lead-free solder considered is 96.5Sn-3.5Ag. The 62Sn-2Ag-36Pb solder is also considered to establish a baseline. These two solder alloys are assumed to obey the Garofalo-Arrhenius steady-state creep constitutive law. The shear stress and shear creep strain hysteresis loops, shear stress history, shear creep strain history, and creep strain density range at the corner solder joint are presented for a better understanding of the thermal-mechanical behavior of the lead-free solder bumped WLCSP on microvia buildup PCB assemblies.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/TEPM.2002.1000483</doi><tpages>8</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 1521-334X |
| ispartof | IEEE transactions on electronics packaging manufacturing, 2002-01, Vol.25 (1), p.51-58 |
| issn | 1521-334X 1558-0822 |
| language | eng |
| recordid | cdi_proquest_miscellaneous_907964981 |
| source | IEEE Electronic Library (IEL) |
| subjects | Applied sciences Assembly Capacitive sensors Chip scale packaging Chips Circuit boards Construction Creep Creep (materials) Electronic equipment and fabrication. Passive components, printed wiring boards, connectics Electronics Environmentally friendly manufacturing techniques Exact sciences and technology History Lead Packages Printed circuits Semiconductor device modeling Soldering Solders Strain Testing, measurement, noise and reliability Thermal stresses Tin base alloys |
| title | Modeling and analysis of 96.5Sn-3.5Ag lead-free solder joints of wafer level chip scale package on buildup microvia printed circuit board |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-12T13%3A56%3A29IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Modeling%20and%20analysis%20of%2096.5Sn-3.5Ag%20lead-free%20solder%20joints%20of%20wafer%20level%20chip%20scale%20package%20on%20buildup%20microvia%20printed%20circuit%20board&rft.jtitle=IEEE%20transactions%20on%20electronics%20packaging%20manufacturing&rft.au=Lau,%20J.H.&rft.date=2002-01&rft.volume=25&rft.issue=1&rft.spage=51&rft.epage=58&rft.pages=51-58&rft.issn=1521-334X&rft.eissn=1558-0822&rft.coden=ITEPFL&rft_id=info:doi/10.1109/TEPM.2002.1000483&rft_dat=%3Cproquest_RIE%3E28356168%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=884432612&rft_id=info:pmid/&rft_ieee_id=1000483&rfr_iscdi=true |