Architecture and Physical Implementation of a Third Generation 65 nm, 16 Core, 32 Thread Chip-Multithreading SPARC Processor

This third-generation Chip-Multithreading (CMT) SPARC processor consists of 16 cores with shared memory architecture and supports a total of 32 main threads plus 32 scout threads. It is targeted for high-performance servers, and is optimized for both single- and multi-threaded applications. The 396...

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Veröffentlicht in:	IEEE journal of solid-state circuits 2009-01, Vol.44 (1), p.7-17
Hauptverfasser:	Konstadinidis, G.K., Tremblay, M., Chaudhry, S., Rashid, M., Lai, P.F., Otaguro, Y., Orginos, Y., Parampalli, S., Steigerwald, M., Gundala, S., Pyapali, R., Rarick, L.D., Elkin, I., Ge, Y., Parulkar, I.
Format:	Artikel
Sprache:	eng
Schlagworte:	Applied sciences Architecture Arrays chip multi-threading (CMT) Circuits clocking Clocks CMOS computer architecture Computers, microcomputers Design. Technologies. Operation analysis. Testing Electronics Exact sciences and technology execute ahead Floating point arithmetic Hardware hardware scout Integrated circuits Integrated circuits by function (including memories and processors) Magnetic and optical mass memories microprocessor Microprocessors multi-core multi-threaded Out of order Pipelines power management register files Registers Robustness Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices SerDes SPARC architecture Storage and reproduction of information synchronous and asynchronous clock domains Throughput throughput computing transactional memory
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