Architecture and Physical Implementation of a Third Generation 65 nm, 16 Core, 32 Thread Chip-Multithreading SPARC Processor
This third-generation Chip-Multithreading (CMT) SPARC processor consists of 16 cores with shared memory architecture and supports a total of 32 main threads plus 32 scout threads. It is targeted for high-performance servers, and is optimized for both single- and multi-threaded applications. The 396...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 2009-01, Vol.44 (1), p.7-17 |
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| creator | Konstadinidis, G.K. Tremblay, M. Chaudhry, S. Rashid, M. Lai, P.F. Otaguro, Y. Orginos, Y. Parampalli, S. Steigerwald, M. Gundala, S. Pyapali, R. Rarick, L.D. Elkin, I. Ge, Y. Parulkar, I. |
| description | This third-generation Chip-Multithreading (CMT) SPARC processor consists of 16 cores with shared memory architecture and supports a total of 32 main threads plus 32 scout threads. It is targeted for high-performance servers, and is optimized for both single- and multi-threaded applications. The 396 mm 2 chip is fabricated in an 11 metal layer 65-nm CMOS process and operates at a nominal frequency of 2.3 GHz, consuming a maximum power of 250 W at 1.2 V. This paper provides an overview of the architectural highlights and describes the physical implementation challenges and solutions including circuit innovations in memory arrays, register files, and floating-point hardware that boost the performance and circuit robustness with low area overhead. |
| doi_str_mv | 10.1109/JSSC.2008.2007144 |
| format | Article |
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It is targeted for high-performance servers, and is optimized for both single- and multi-threaded applications. The 396 mm 2 chip is fabricated in an 11 metal layer 65-nm CMOS process and operates at a nominal frequency of 2.3 GHz, consuming a maximum power of 250 W at 1.2 V. This paper provides an overview of the architectural highlights and describes the physical implementation challenges and solutions including circuit innovations in memory arrays, register files, and floating-point hardware that boost the performance and circuit robustness with low area overhead.</description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/JSSC.2008.2007144</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Architecture ; Arrays ; chip multi-threading (CMT) ; Circuits ; clocking ; Clocks ; CMOS ; computer architecture ; Computers, microcomputers ; Design. Technologies. Operation analysis. Testing ; Electronics ; Exact sciences and technology ; execute ahead ; Floating point arithmetic ; Hardware ; hardware scout ; Integrated circuits ; Integrated circuits by function (including memories and processors) ; Magnetic and optical mass memories ; microprocessor ; Microprocessors ; multi-core ; multi-threaded ; Out of order ; Pipelines ; power management ; register files ; Registers ; Robustness ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; SerDes ; SPARC architecture ; Storage and reproduction of information ; synchronous and asynchronous clock domains ; Throughput ; throughput computing ; transactional memory</subject><ispartof>IEEE journal of solid-state circuits, 2009-01, Vol.44 (1), p.7-17</ispartof><rights>2009 INIST-CNRS</rights><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. 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It is targeted for high-performance servers, and is optimized for both single- and multi-threaded applications. The 396 mm 2 chip is fabricated in an 11 metal layer 65-nm CMOS process and operates at a nominal frequency of 2.3 GHz, consuming a maximum power of 250 W at 1.2 V. This paper provides an overview of the architectural highlights and describes the physical implementation challenges and solutions including circuit innovations in memory arrays, register files, and floating-point hardware that boost the performance and circuit robustness with low area overhead.</description><subject>Applied sciences</subject><subject>Architecture</subject><subject>Arrays</subject><subject>chip multi-threading (CMT)</subject><subject>Circuits</subject><subject>clocking</subject><subject>Clocks</subject><subject>CMOS</subject><subject>computer architecture</subject><subject>Computers, microcomputers</subject><subject>Design. Technologies. Operation analysis. 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It is targeted for high-performance servers, and is optimized for both single- and multi-threaded applications. The 396 mm 2 chip is fabricated in an 11 metal layer 65-nm CMOS process and operates at a nominal frequency of 2.3 GHz, consuming a maximum power of 250 W at 1.2 V. This paper provides an overview of the architectural highlights and describes the physical implementation challenges and solutions including circuit innovations in memory arrays, register files, and floating-point hardware that boost the performance and circuit robustness with low area overhead.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/JSSC.2008.2007144</doi><tpages>11</tpages></addata></record> |
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| subjects | Applied sciences Architecture Arrays chip multi-threading (CMT) Circuits clocking Clocks CMOS computer architecture Computers, microcomputers Design. Technologies. Operation analysis. Testing Electronics Exact sciences and technology execute ahead Floating point arithmetic Hardware hardware scout Integrated circuits Integrated circuits by function (including memories and processors) Magnetic and optical mass memories microprocessor Microprocessors multi-core multi-threaded Out of order Pipelines power management register files Registers Robustness Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices SerDes SPARC architecture Storage and reproduction of information synchronous and asynchronous clock domains Throughput throughput computing transactional memory |
| title | Architecture and Physical Implementation of a Third Generation 65 nm, 16 Core, 32 Thread Chip-Multithreading SPARC Processor |
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