Compact Modeling of Lateral Nonuniform Doping in High-Voltage MOSFETs
This paper reports on the detailed analysis and modeling of lateral nonuniform doping present in intrinsic MOS channel of high-voltage (HV) MOSFETs, e.g., vertical (VDMOS) and lateral diffused MOS (LDMOS). It is shown that conventional long-channel MOSFET models using uniform lateral doping can neve...
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| Veröffentlicht in: | IEEE transactions on electron devices 2007-06, Vol.54 (6), p.1527-1539 |
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| container_title | IEEE transactions on electron devices |
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| creator | Chauhan, Y.S. Krummenacher, F. Gillon, R. Bakeroot, B. Declercq, M.J. Ionescu, A.M. |
| description | This paper reports on the detailed analysis and modeling of lateral nonuniform doping present in intrinsic MOS channel of high-voltage (HV) MOSFETs, e.g., vertical (VDMOS) and lateral diffused MOS (LDMOS). It is shown that conventional long-channel MOSFET models using uniform lateral doping can never correctly model the capacitance behavior of these devices. A new analytical compact model for lateral nonuniformly doped MOSFET is reported. The intrinsic nonuniformly doped MOS model is first validated on numerical simulation and then on measured characteristics of VDMOS and LDMOS transistors including the drift region. The model shows good results in the dc and, most importantly, in the ac regime, especially in simulating the peaks on C GD , C GS , and C GG capacitances. This new model improves the accuracy of HV MOS models, especially output characteristics and during transient response (i.e., amplitude and position of peaks, as well as slope of capacitances). |
| doi_str_mv | 10.1109/TED.2007.896597 |
| format | Article |
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It is shown that conventional long-channel MOSFET models using uniform lateral doping can never correctly model the capacitance behavior of these devices. A new analytical compact model for lateral nonuniformly doped MOSFET is reported. The intrinsic nonuniformly doped MOS model is first validated on numerical simulation and then on measured characteristics of VDMOS and LDMOS transistors including the drift region. The model shows good results in the dc and, most importantly, in the ac regime, especially in simulating the peaks on C GD , C GS , and C GG capacitances. This new model improves the accuracy of HV MOS models, especially output characteristics and during transient response (i.e., amplitude and position of peaks, as well as slope of capacitances).</description><identifier>ISSN: 0018-9383</identifier><identifier>EISSN: 1557-9646</identifier><identifier>DOI: 10.1109/TED.2007.896597</identifier><identifier>CODEN: IETDAI</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Biological system modeling ; Capacitance ; Channels ; compact model ; Compound structure devices ; Computer simulation ; Devices ; Doping ; drift ; Electronics ; Exact sciences and technology ; high voltage ; Integrated circuit modeling ; lateral diffused MOS (LDMOS) ; lateral doping ; Mathematical models ; Metal oxide semiconductors ; MOSFET ; MOSFETs ; Nonuniform ; Numerical models ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Semiconductor process modeling ; Transistors ; vertical diffused MOS (VDMOS)</subject><ispartof>IEEE transactions on electron devices, 2007-06, Vol.54 (6), p.1527-1539</ispartof><rights>2007 INIST-CNRS</rights><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2007</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c479t-df8ae503b00b4ecd5b3b4a680c0b4256832feaeecb2ac57be17e646ccc1e6f7e3</citedby><cites>FETCH-LOGICAL-c479t-df8ae503b00b4ecd5b3b4a680c0b4256832feaeecb2ac57be17e646ccc1e6f7e3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4215161$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>315,781,785,797,27926,27927,54760</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4215161$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=18798290$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Chauhan, Y.S.</creatorcontrib><creatorcontrib>Krummenacher, F.</creatorcontrib><creatorcontrib>Gillon, R.</creatorcontrib><creatorcontrib>Bakeroot, B.</creatorcontrib><creatorcontrib>Declercq, M.J.</creatorcontrib><creatorcontrib>Ionescu, A.M.</creatorcontrib><title>Compact Modeling of Lateral Nonuniform Doping in High-Voltage MOSFETs</title><title>IEEE transactions on electron devices</title><addtitle>TED</addtitle><description>This paper reports on the detailed analysis and modeling of lateral nonuniform doping present in intrinsic MOS channel of high-voltage (HV) MOSFETs, e.g., vertical (VDMOS) and lateral diffused MOS (LDMOS). It is shown that conventional long-channel MOSFET models using uniform lateral doping can never correctly model the capacitance behavior of these devices. A new analytical compact model for lateral nonuniformly doped MOSFET is reported. The intrinsic nonuniformly doped MOS model is first validated on numerical simulation and then on measured characteristics of VDMOS and LDMOS transistors including the drift region. The model shows good results in the dc and, most importantly, in the ac regime, especially in simulating the peaks on C GD , C GS , and C GG capacitances. This new model improves the accuracy of HV MOS models, especially output characteristics and during transient response (i.e., amplitude and position of peaks, as well as slope of capacitances).</description><subject>Applied sciences</subject><subject>Biological system modeling</subject><subject>Capacitance</subject><subject>Channels</subject><subject>compact model</subject><subject>Compound structure devices</subject><subject>Computer simulation</subject><subject>Devices</subject><subject>Doping</subject><subject>drift</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>high voltage</subject><subject>Integrated circuit modeling</subject><subject>lateral diffused MOS (LDMOS)</subject><subject>lateral doping</subject><subject>Mathematical models</subject><subject>Metal oxide semiconductors</subject><subject>MOSFET</subject><subject>MOSFETs</subject><subject>Nonuniform</subject><subject>Numerical models</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Semiconductor process modeling</subject><subject>Transistors</subject><subject>vertical diffused MOS (VDMOS)</subject><issn>0018-9383</issn><issn>1557-9646</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2007</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNqFkTlPA0EMhUcIJMJRU9CskIBqw9xHiZJwSAEKjnY0O_GGRZudMLMp-PdMFAQSBVSW7c9Pth9CRwQPCcHm4mkyHlKM1VAbKYzaQgMihCqN5HIbDTAmujRMs120l9JbTiXndIAmo7BYOt8Xd2EGbdPNi1AXU9dDdG1xH7pV19QhLopxWK6bTVfcNPPX8iW0vZtDcffweDV5Sgdop3ZtgsOvuI-ec3l0U04frm9Hl9PSc2X6clZrBwKzCuOKg5-JilXcSY19zqmQmtEaHICvqPNCVUAU5PW99wRkrYDto_ON7jKG9xWk3i6a5KFtXQdhlazBTFJFGP2X1EpglX-iMnn2J8k4x0wxksGTX-BbWMUu32u1ZMpooXCGLjaQjyGlCLVdxmbh4ocl2K59stknu_bJbnzKE6dfsi5519bRdb5JP2M6K1OzVj7ecA0AfLc5JYJIwj4BbOGZqg</recordid><startdate>20070601</startdate><enddate>20070601</enddate><creator>Chauhan, Y.S.</creator><creator>Krummenacher, F.</creator><creator>Gillon, R.</creator><creator>Bakeroot, B.</creator><creator>Declercq, M.J.</creator><creator>Ionescu, A.M.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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Solid state devices</topic><topic>Semiconductor process modeling</topic><topic>Transistors</topic><topic>vertical diffused MOS (VDMOS)</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Chauhan, Y.S.</creatorcontrib><creatorcontrib>Krummenacher, F.</creatorcontrib><creatorcontrib>Gillon, R.</creatorcontrib><creatorcontrib>Bakeroot, B.</creatorcontrib><creatorcontrib>Declercq, M.J.</creatorcontrib><creatorcontrib>Ionescu, A.M.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005–Present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE transactions on electron devices</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Chauhan, Y.S.</au><au>Krummenacher, F.</au><au>Gillon, R.</au><au>Bakeroot, B.</au><au>Declercq, M.J.</au><au>Ionescu, A.M.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Compact Modeling of Lateral Nonuniform Doping in High-Voltage MOSFETs</atitle><jtitle>IEEE transactions on electron devices</jtitle><stitle>TED</stitle><date>2007-06-01</date><risdate>2007</risdate><volume>54</volume><issue>6</issue><spage>1527</spage><epage>1539</epage><pages>1527-1539</pages><issn>0018-9383</issn><eissn>1557-9646</eissn><coden>IETDAI</coden><abstract>This paper reports on the detailed analysis and modeling of lateral nonuniform doping present in intrinsic MOS channel of high-voltage (HV) MOSFETs, e.g., vertical (VDMOS) and lateral diffused MOS (LDMOS). It is shown that conventional long-channel MOSFET models using uniform lateral doping can never correctly model the capacitance behavior of these devices. A new analytical compact model for lateral nonuniformly doped MOSFET is reported. The intrinsic nonuniformly doped MOS model is first validated on numerical simulation and then on measured characteristics of VDMOS and LDMOS transistors including the drift region. The model shows good results in the dc and, most importantly, in the ac regime, especially in simulating the peaks on C GD , C GS , and C GG capacitances. This new model improves the accuracy of HV MOS models, especially output characteristics and during transient response (i.e., amplitude and position of peaks, as well as slope of capacitances).</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/TED.2007.896597</doi><tpages>13</tpages></addata></record> |
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| subjects | Applied sciences Biological system modeling Capacitance Channels compact model Compound structure devices Computer simulation Devices Doping drift Electronics Exact sciences and technology high voltage Integrated circuit modeling lateral diffused MOS (LDMOS) lateral doping Mathematical models Metal oxide semiconductors MOSFET MOSFETs Nonuniform Numerical models Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Semiconductor process modeling Transistors vertical diffused MOS (VDMOS) |
| title | Compact Modeling of Lateral Nonuniform Doping in High-Voltage MOSFETs |
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