A cost-effective approach to the design and layout of a 14-b current-steering DAC macrocell
This brief discusses the economical design of a 14-b current-steering digital-to-analog converter (DAC) macrocell for integration with other analog and digital macrocells in a system-on-chip (SOC). The DAC design is targeted for a standard 0.13-/spl mu/m six-metal single-poly CMOS process. A novel a...
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| Veröffentlicht in: | IEEE transactions on circuits and systems. 1, Fundamental theory and applications Fundamental theory and applications, 2004-01, Vol.51 (1), p.196-200 |
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| container_title | IEEE transactions on circuits and systems. 1, Fundamental theory and applications |
| container_volume | 51 |
| creator | Starzyk, J.A. Mohn, R.P. Liang Jing |
| description | This brief discusses the economical design of a 14-b current-steering digital-to-analog converter (DAC) macrocell for integration with other analog and digital macrocells in a system-on-chip (SOC). The DAC design is targeted for a standard 0.13-/spl mu/m six-metal single-poly CMOS process. A novel algorithm sets the switching order of individual current sources and minimizes systematic mismatch errors. The design approach minimizes total fabrication cost of the SOC without a loss to specified DAC design requirements. Total macrocell design area is 2.9 mm/sup 2/. |
| doi_str_mv | 10.1109/TCSI.2003.821282 |
| format | Article |
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| identifier | ISSN: 1549-8328 |
| ispartof | IEEE transactions on circuits and systems. 1, Fundamental theory and applications, 2004-01, Vol.51 (1), p.196-200 |
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| source | IEEE Electronic Library (IEL) |
| subjects | Analog to digital converters Circuits CMOS CMOS process Cost engineering Costs Design engineering Digital-analog conversion Dynamic range Economics Fabrication Linearity Macrocell networks Process design Switching System-on-a-chip Temperature |
| title | A cost-effective approach to the design and layout of a 14-b current-steering DAC macrocell |
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