High work-function metal gate and high-κ dielectrics for charge trap flash memory device applications
We report the impact of high work-function ( Phi sub(M)) metal gate and high- Kappa dielectrics on memory properties of NAND-type charge trap Flash (CTF) memory devices. In this paper, theoretical and experimental studies show that high Phi sub(M) gate and high permittivity (high- Kappa ) dielectric...
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| Veröffentlicht in: | IEEE transactions on electron devices 2005-12, Vol.52 (12), p.2654-2659 |
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| container_title | IEEE transactions on electron devices |
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| creator | JEON, Sanghun JEONG HEE HAN JUNG HOON LEE CHOI, Sangmoo HWANG, Hyunsang KIM, Chungwoo |
| description | We report the impact of high work-function ( Phi sub(M)) metal gate and high- Kappa dielectrics on memory properties of NAND-type charge trap Flash (CTF) memory devices. In this paper, theoretical and experimental studies show that high Phi sub(M) gate and high permittivity (high- Kappa ) dielectrics play a key role in eliminating electron back tunneling though the blocking dielectric during the erase operation. Techniques to improve erase efficiency of CTF memory devices with a fixed metal gate by employing various chemicals and structures are introduced and those mechanisms are discussed. Though process optimization of high Phi sub(M) gate and high- Kappa materials, enhanced CTF device characteristics such as high speed, large memory window, and good reliability characteristics of the CTF devices are obtained. |
| doi_str_mv | 10.1109/ted.2005.859691 |
| format | Article |
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In this paper, theoretical and experimental studies show that high Phi sub(M) gate and high permittivity (high- Kappa ) dielectrics play a key role in eliminating electron back tunneling though the blocking dielectric during the erase operation. Techniques to improve erase efficiency of CTF memory devices with a fixed metal gate by employing various chemicals and structures are introduced and those mechanisms are discussed. Though process optimization of high Phi sub(M) gate and high- Kappa materials, enhanced CTF device characteristics such as high speed, large memory window, and good reliability characteristics of the CTF devices are obtained.</description><identifier>ISSN: 0018-9383</identifier><identifier>EISSN: 1557-9646</identifier><identifier>DOI: 10.1109/ted.2005.859691</identifier><identifier>CODEN: IETDAI</identifier><language>eng</language><publisher>New York, NY: Institute of Electrical and Electronics Engineers</publisher><subject>Applied sciences ; Charge ; Data storage ; Design. Technologies. Operation analysis. Testing ; Devices ; Dielectrics ; Electronics ; Exact sciences and technology ; Gates ; High speed ; Integrated circuits ; Integrated circuits by function (including memories and processors) ; Magnetic and optical mass memories ; Memory devices ; Optimization ; Semiconductor electronics. Microelectronics. Optoelectronics. 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In this paper, theoretical and experimental studies show that high Phi sub(M) gate and high permittivity (high- Kappa ) dielectrics play a key role in eliminating electron back tunneling though the blocking dielectric during the erase operation. Techniques to improve erase efficiency of CTF memory devices with a fixed metal gate by employing various chemicals and structures are introduced and those mechanisms are discussed. Though process optimization of high Phi sub(M) gate and high- Kappa materials, enhanced CTF device characteristics such as high speed, large memory window, and good reliability characteristics of the CTF devices are obtained.</description><subject>Applied sciences</subject><subject>Charge</subject><subject>Data storage</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Devices</subject><subject>Dielectrics</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Gates</subject><subject>High speed</subject><subject>Integrated circuits</subject><subject>Integrated circuits by function (including memories and processors)</subject><subject>Magnetic and optical mass memories</subject><subject>Memory devices</subject><subject>Optimization</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. 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Technologies. Operation analysis. Testing</topic><topic>Devices</topic><topic>Dielectrics</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Gates</topic><topic>High speed</topic><topic>Integrated circuits</topic><topic>Integrated circuits by function (including memories and processors)</topic><topic>Magnetic and optical mass memories</topic><topic>Memory devices</topic><topic>Optimization</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Storage and reproduction of information</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>JEON, Sanghun</creatorcontrib><creatorcontrib>JEONG HEE HAN</creatorcontrib><creatorcontrib>JUNG HOON LEE</creatorcontrib><creatorcontrib>CHOI, Sangmoo</creatorcontrib><creatorcontrib>HWANG, Hyunsang</creatorcontrib><creatorcontrib>KIM, Chungwoo</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE transactions on electron devices</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>JEON, Sanghun</au><au>JEONG HEE HAN</au><au>JUNG HOON LEE</au><au>CHOI, Sangmoo</au><au>HWANG, Hyunsang</au><au>KIM, Chungwoo</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>High work-function metal gate and high-κ dielectrics for charge trap flash memory device applications</atitle><jtitle>IEEE transactions on electron devices</jtitle><date>2005-12-01</date><risdate>2005</risdate><volume>52</volume><issue>12</issue><spage>2654</spage><epage>2659</epage><pages>2654-2659</pages><issn>0018-9383</issn><eissn>1557-9646</eissn><coden>IETDAI</coden><abstract>We report the impact of high work-function ( Phi sub(M)) metal gate and high- Kappa dielectrics on memory properties of NAND-type charge trap Flash (CTF) memory devices. In this paper, theoretical and experimental studies show that high Phi sub(M) gate and high permittivity (high- Kappa ) dielectrics play a key role in eliminating electron back tunneling though the blocking dielectric during the erase operation. Techniques to improve erase efficiency of CTF memory devices with a fixed metal gate by employing various chemicals and structures are introduced and those mechanisms are discussed. Though process optimization of high Phi sub(M) gate and high- Kappa materials, enhanced CTF device characteristics such as high speed, large memory window, and good reliability characteristics of the CTF devices are obtained.</abstract><cop>New York, NY</cop><pub>Institute of Electrical and Electronics Engineers</pub><doi>10.1109/ted.2005.859691</doi><tpages>6</tpages></addata></record> |
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| ispartof | IEEE transactions on electron devices, 2005-12, Vol.52 (12), p.2654-2659 |
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| source | IEEE Electronic Library (IEL) |
| subjects | Applied sciences Charge Data storage Design. Technologies. Operation analysis. Testing Devices Dielectrics Electronics Exact sciences and technology Gates High speed Integrated circuits Integrated circuits by function (including memories and processors) Magnetic and optical mass memories Memory devices Optimization Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Storage and reproduction of information |
| title | High work-function metal gate and high-κ dielectrics for charge trap flash memory device applications |
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