Dynamic state-retention flip-flop for fine-grained power gating with small design and power overhead
Fine-grained power gating is the rigorous application of sleep transistor scheme to reduce stand-by power consumption in idle circuit blocks. Small circuit blocks are suspended for a short time while they are temporarily not needed. A sense-amplifier-based state retention flip-flop is proposed, that...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 2006-07, Vol.41 (7), p.1654-1661, Article 1654 |
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| container_title | IEEE journal of solid-state circuits |
| container_volume | 41 |
| creator | Henzler, S. Georgakos, G. Eireiner, M. Nirschl, T. Pacha, C. Berthold, J. Schmitt-Landsiedel, D. |
| description | Fine-grained power gating is the rigorous application of sleep transistor scheme to reduce stand-by power consumption in idle circuit blocks. Small circuit blocks are suspended for a short time while they are temporarily not needed. A sense-amplifier-based state retention flip-flop is proposed, that preserves the logical state of the circuit during these short idle periods. This dynamic state retention flip-flop requires neither additional control signals nor an additional power supply for its state retention functionality. An integration into a standard design flow is possible without any modifications. The tradeoff between propagation delay and retention time is derived analytically. Retention times in the range of milliseconds can be achieved with D-to-Q delays of 100 ps to 200 ps |
| doi_str_mv | 10.1109/JSSC.2006.873218 |
| format | Article |
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Small circuit blocks are suspended for a short time while they are temporarily not needed. A sense-amplifier-based state retention flip-flop is proposed, that preserves the logical state of the circuit during these short idle periods. This dynamic state retention flip-flop requires neither additional control signals nor an additional power supply for its state retention functionality. An integration into a standard design flow is possible without any modifications. The tradeoff between propagation delay and retention time is derived analytically. Retention times in the range of milliseconds can be achieved with D-to-Q delays of 100 ps to 200 ps</description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/JSSC.2006.873218</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Amplifiers ; Applied sciences ; Circuit properties ; Circuits ; Delay ; Digital circuits ; Dynamics ; Electric, optical and optoelectronic circuits ; Electronic circuits ; Electronic equipment and fabrication. Passive components, printed wiring boards, connectics ; Electronics ; Energy consumption ; Exact sciences and technology ; Flip-flops ; Gating and risering ; Leakage current ; Leakage reduction ; Logic circuits ; low power ; Mathematical analysis ; MTCMOS ; Power consumption ; power gating ; Power supplies ; Preserves ; Propagation delay ; Rails ; retention flip-flop ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; sleep transistor ; state retention ; Subthreshold current ; System-on-a-chip ; Transistors ; Tunneling</subject><ispartof>IEEE journal of solid-state circuits, 2006-07, Vol.41 (7), p.1654-1661, Article 1654</ispartof><rights>2006 INIST-CNRS</rights><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2006</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c352t-2a5f32554c96ae75168acc79d08ee1bf8daf28f4163e640f604d4b55f8f38bc33</citedby><cites>FETCH-LOGICAL-c352t-2a5f32554c96ae75168acc79d08ee1bf8daf28f4163e640f604d4b55f8f38bc33</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1644877$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,314,776,780,785,786,792,23909,23910,25118,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1644877$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=17962240$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Henzler, S.</creatorcontrib><creatorcontrib>Georgakos, G.</creatorcontrib><creatorcontrib>Eireiner, M.</creatorcontrib><creatorcontrib>Nirschl, T.</creatorcontrib><creatorcontrib>Pacha, C.</creatorcontrib><creatorcontrib>Berthold, J.</creatorcontrib><creatorcontrib>Schmitt-Landsiedel, D.</creatorcontrib><title>Dynamic state-retention flip-flop for fine-grained power gating with small design and power overhead</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description>Fine-grained power gating is the rigorous application of sleep transistor scheme to reduce stand-by power consumption in idle circuit blocks. Small circuit blocks are suspended for a short time while they are temporarily not needed. A sense-amplifier-based state retention flip-flop is proposed, that preserves the logical state of the circuit during these short idle periods. This dynamic state retention flip-flop requires neither additional control signals nor an additional power supply for its state retention functionality. An integration into a standard design flow is possible without any modifications. The tradeoff between propagation delay and retention time is derived analytically. Retention times in the range of milliseconds can be achieved with D-to-Q delays of 100 ps to 200 ps</description><subject>Amplifiers</subject><subject>Applied sciences</subject><subject>Circuit properties</subject><subject>Circuits</subject><subject>Delay</subject><subject>Digital circuits</subject><subject>Dynamics</subject><subject>Electric, optical and optoelectronic circuits</subject><subject>Electronic circuits</subject><subject>Electronic equipment and fabrication. Passive components, printed wiring boards, connectics</subject><subject>Electronics</subject><subject>Energy consumption</subject><subject>Exact sciences and technology</subject><subject>Flip-flops</subject><subject>Gating and risering</subject><subject>Leakage current</subject><subject>Leakage reduction</subject><subject>Logic circuits</subject><subject>low power</subject><subject>Mathematical analysis</subject><subject>MTCMOS</subject><subject>Power consumption</subject><subject>power gating</subject><subject>Power supplies</subject><subject>Preserves</subject><subject>Propagation delay</subject><subject>Rails</subject><subject>retention flip-flop</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>sleep transistor</subject><subject>state retention</subject><subject>Subthreshold current</subject><subject>System-on-a-chip</subject><subject>Transistors</subject><subject>Tunneling</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2006</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNp9kU1rVDEUhoMoOFb3gpsgiKs75vvmLmX8qFJwUQV3IZN7Mk3JJNck09J_b4apFLpwdTjkOW8Oz0HoNSVrSsn04fvl5WbNCFFrPXJG9RO0olLqgY7891O0IoTqYervz9GLWq97K4SmKzR_ukt2HxyuzTYYCjRILeSEfQzL4GNesM8F-5Bg2BXby4yXfAsF72wLaYdvQ7vCdW9jxDPUsEvYpn9IvoFyBXZ-iZ55Gyu8uq9n6NeXzz8358PFj6_fNh8vBsclawOz0nMmpXCTsjBKqrR1bpxmogHo1uvZeqa9oIqDEsQrImaxldJrz_XWcX6G3p9yl5L_HKA2sw_VQYw2QT5UoyfFCCNcdvLtI_I6H0rqy5mJMjJxJmiHyAlyJddawJulhL0td4YSc5RujtLNUbo5Se8j7-5zbXU2-mKTC_VhbuwbMEE6px5Fu9AP0MW3Ljn-74M3p8EAAA-5ql9zHPlf6Aacqw</recordid><startdate>20060701</startdate><enddate>20060701</enddate><creator>Henzler, S.</creator><creator>Georgakos, G.</creator><creator>Eireiner, M.</creator><creator>Nirschl, T.</creator><creator>Pacha, C.</creator><creator>Berthold, J.</creator><creator>Schmitt-Landsiedel, D.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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Passive components, printed wiring boards, connectics</topic><topic>Electronics</topic><topic>Energy consumption</topic><topic>Exact sciences and technology</topic><topic>Flip-flops</topic><topic>Gating and risering</topic><topic>Leakage current</topic><topic>Leakage reduction</topic><topic>Logic circuits</topic><topic>low power</topic><topic>Mathematical analysis</topic><topic>MTCMOS</topic><topic>Power consumption</topic><topic>power gating</topic><topic>Power supplies</topic><topic>Preserves</topic><topic>Propagation delay</topic><topic>Rails</topic><topic>retention flip-flop</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>sleep transistor</topic><topic>state retention</topic><topic>Subthreshold current</topic><topic>System-on-a-chip</topic><topic>Transistors</topic><topic>Tunneling</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Henzler, S.</creatorcontrib><creatorcontrib>Georgakos, G.</creatorcontrib><creatorcontrib>Eireiner, M.</creatorcontrib><creatorcontrib>Nirschl, T.</creatorcontrib><creatorcontrib>Pacha, C.</creatorcontrib><creatorcontrib>Berthold, J.</creatorcontrib><creatorcontrib>Schmitt-Landsiedel, D.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Henzler, S.</au><au>Georgakos, G.</au><au>Eireiner, M.</au><au>Nirschl, T.</au><au>Pacha, C.</au><au>Berthold, J.</au><au>Schmitt-Landsiedel, D.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Dynamic state-retention flip-flop for fine-grained power gating with small design and power overhead</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>2006-07-01</date><risdate>2006</risdate><volume>41</volume><issue>7</issue><spage>1654</spage><epage>1661</epage><pages>1654-1661</pages><artnum>1654</artnum><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract>Fine-grained power gating is the rigorous application of sleep transistor scheme to reduce stand-by power consumption in idle circuit blocks. Small circuit blocks are suspended for a short time while they are temporarily not needed. A sense-amplifier-based state retention flip-flop is proposed, that preserves the logical state of the circuit during these short idle periods. This dynamic state retention flip-flop requires neither additional control signals nor an additional power supply for its state retention functionality. An integration into a standard design flow is possible without any modifications. The tradeoff between propagation delay and retention time is derived analytically. Retention times in the range of milliseconds can be achieved with D-to-Q delays of 100 ps to 200 ps</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/JSSC.2006.873218</doi><tpages>8</tpages></addata></record> |
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| ispartof | IEEE journal of solid-state circuits, 2006-07, Vol.41 (7), p.1654-1661, Article 1654 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Amplifiers Applied sciences Circuit properties Circuits Delay Digital circuits Dynamics Electric, optical and optoelectronic circuits Electronic circuits Electronic equipment and fabrication. Passive components, printed wiring boards, connectics Electronics Energy consumption Exact sciences and technology Flip-flops Gating and risering Leakage current Leakage reduction Logic circuits low power Mathematical analysis MTCMOS Power consumption power gating Power supplies Preserves Propagation delay Rails retention flip-flop Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices sleep transistor state retention Subthreshold current System-on-a-chip Transistors Tunneling |
| title | Dynamic state-retention flip-flop for fine-grained power gating with small design and power overhead |
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