Dynamic state-retention flip-flop for fine-grained power gating with small design and power overhead

Dynamic state-retention flip-flop for fine-grained power gating with small design and power overhead

Fine-grained power gating is the rigorous application of sleep transistor scheme to reduce stand-by power consumption in idle circuit blocks. Small circuit blocks are suspended for a short time while they are temporarily not needed. A sense-amplifier-based state retention flip-flop is proposed, that...

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Veröffentlicht in:IEEE journal of solid-state circuits 2006-07, Vol.41 (7), p.1654-1661, Article 1654
Hauptverfasser: Henzler, S., Georgakos, G., Eireiner, M., Nirschl, T., Pacha, C., Berthold, J., Schmitt-Landsiedel, D.
Format: Artikel
Sprache:eng
Schlagworte:
Amplifiers
Applied sciences
Circuit properties
Circuits
Delay
Digital circuits
Dynamics
Electric, optical and optoelectronic circuits
Electronic circuits
Electronic equipment and fabrication. Passive components, printed wiring boards, connectics
Electronics
Energy consumption
Exact sciences and technology
Flip-flops
Gating and risering
Leakage current
Leakage reduction
Logic circuits
low power
Mathematical analysis
MTCMOS
Power consumption
power gating
Power supplies
Preserves
Propagation delay
Rails
retention flip-flop
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
sleep transistor
state retention
Subthreshold current
System-on-a-chip
Transistors
Tunneling
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Beschreibung
Zusammenfassung:Fine-grained power gating is the rigorous application of sleep transistor scheme to reduce stand-by power consumption in idle circuit blocks. Small circuit blocks are suspended for a short time while they are temporarily not needed. A sense-amplifier-based state retention flip-flop is proposed, that preserves the logical state of the circuit during these short idle periods. This dynamic state retention flip-flop requires neither additional control signals nor an additional power supply for its state retention functionality. An integration into a standard design flow is possible without any modifications. The tradeoff between propagation delay and retention time is derived analytically. Retention times in the range of milliseconds can be achieved with D-to-Q delays of 100 ps to 200 ps
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2006.873218