Impact of “terminal effect” on Cu electrochemical deposition: Filling capability for different metallization options
The 300 mm wafer copper electrochemical deposition (ECD) process for dual damascene metallization of semiconductor advanced interconnects is critically reviewed and the breakthroughs that enable further scaling of this process are examined. Special emphasis is placed on analyzing the critical issues...
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| Veröffentlicht in: | Microelectronic engineering 2011-05, Vol.88 (5), p.754-759 |
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| container_title | Microelectronic engineering |
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| creator | Armini, Silvia Tokei, Zsolt Volders, Henny El-Mekki, Zaid Radisic, Aleksandar Beyer, Gerald Ruythooren, Wouter Vereecken, Philippe M. |
| description | The 300
mm wafer copper electrochemical deposition (ECD) process for dual damascene metallization of semiconductor advanced interconnects is critically reviewed and the breakthroughs that enable further scaling of this process are examined. Special emphasis is placed on analyzing the critical issues, such as barrier/seed options, terminal effect and future plating prospects for this technology. The smallest plateable feature size values are estimated for different metallization integration schemes, such as conventional Physical Vapor Deposited (PVD) TaN/Ta/Cu, hybrid RuTa/Cu, CuMn (8%) self-forming barrier/seed, and Plasma-Enhanced Atomic Layer Deposition (PEALD) Ru, limiting the allowed maximum sheet resistance to 14
Ohms/sq for the Cu-based seeds and the effective maximum filling aspect ratio to 5–6. |
| doi_str_mv | 10.1016/j.mee.2010.08.013 |
| format | Article |
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mm wafer copper electrochemical deposition (ECD) process for dual damascene metallization of semiconductor advanced interconnects is critically reviewed and the breakthroughs that enable further scaling of this process are examined. Special emphasis is placed on analyzing the critical issues, such as barrier/seed options, terminal effect and future plating prospects for this technology. The smallest plateable feature size values are estimated for different metallization integration schemes, such as conventional Physical Vapor Deposited (PVD) TaN/Ta/Cu, hybrid RuTa/Cu, CuMn (8%) self-forming barrier/seed, and Plasma-Enhanced Atomic Layer Deposition (PEALD) Ru, limiting the allowed maximum sheet resistance to 14
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| ispartof | Microelectronic engineering, 2011-05, Vol.88 (5), p.754-759 |
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| source | Elsevier ScienceDirect Journals |
| subjects | Applied sciences Barriers Copper Cross-disciplinary physics: materials science rheology Deposition Design. Technologies. Operation analysis. Testing Direct on barrier plating Electrodeposition, electroplating Electronics Exact sciences and technology Integrated circuits Materials science Metallization options Metallizing Methods of deposition of films and coatings film growth and epitaxy Microelectronic fabrication (materials and surfaces technology) Physical vapor deposition Physics Seeds Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Semiconductors Terminal effect Terminals Vapor phase epitaxy growth from vapor phase |
| title | Impact of “terminal effect” on Cu electrochemical deposition: Filling capability for different metallization options |
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