Si passivation for Ge pMOSFETs: Impact of Si cap growth conditions
► Impact of Si cap Ge passivation pn Ge pMOSFETs performances. ► Impact of RPCVD Si growth process conditions on Si crystallinity and Ge segregation. ► Offers the best route for Ge passivation. Ultra thin Si cap growth by Reduced Pressure Chemical Vapor Deposition on relaxed Ge substrates is detaile...
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| Veröffentlicht in: | Solid-state electronics 2011-06, Vol.60 (1), p.116-121 |
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| creator | Vincent, B. Loo, R. Vandervorst, W. Delmotte, J. Douhard, B. Valev, V.K. Vanbel, M. Verbiest, T. Rip, J. Brijs, B. Conard, T. Claypool, C. Takeuchi, S. Zaima, S. Mitard, J. De Jaeger, B. Dekoster, J. Caymax, M. |
| description | ► Impact of Si cap Ge passivation pn Ge pMOSFETs performances. ► Impact of RPCVD Si growth process conditions on Si crystallinity and Ge segregation. ► Offers the best route for Ge passivation.
Ultra thin Si cap growth by Reduced Pressure Chemical Vapor Deposition on relaxed Ge substrates is detailed in this paper for Ge pMOSFET (Metal Oxide Semiconductor Field Effect Transistors) passivation purposes. A cross calibration of different measurement techniques is first proposed to perfectly monitor Si monolayers thickness deposited on Ge substrates. Different characteristics, impacting Ge pMOSFETs device performances, are next detailed for various Si cap growth processes using different Si precursors: DiChloroSilane (DCS), silane and trisilane. The critical Si thickness of plastic relaxation has been determined at 12 monolayers. Presence of point defects has been identified for very low growth temperature as 350
°C. Ge–Si intermixing, caused by a Ge segregation mechanism, is strongly reduced by the use of trisilane as Si precursor at low temperatures. |
| doi_str_mv | 10.1016/j.sse.2011.01.049 |
| format | Article |
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Ultra thin Si cap growth by Reduced Pressure Chemical Vapor Deposition on relaxed Ge substrates is detailed in this paper for Ge pMOSFET (Metal Oxide Semiconductor Field Effect Transistors) passivation purposes. A cross calibration of different measurement techniques is first proposed to perfectly monitor Si monolayers thickness deposited on Ge substrates. Different characteristics, impacting Ge pMOSFETs device performances, are next detailed for various Si cap growth processes using different Si precursors: DiChloroSilane (DCS), silane and trisilane. The critical Si thickness of plastic relaxation has been determined at 12 monolayers. Presence of point defects has been identified for very low growth temperature as 350
°C. Ge–Si intermixing, caused by a Ge segregation mechanism, is strongly reduced by the use of trisilane as Si precursor at low temperatures.</description><identifier>ISSN: 0038-1101</identifier><identifier>EISSN: 1879-2405</identifier><identifier>DOI: 10.1016/j.sse.2011.01.049</identifier><language>eng</language><publisher>Kidlington: Elsevier Ltd</publisher><subject>Applied sciences ; Chemical vapor deposition (including plasma-enhanced cvd, mocvd, etc.) ; Cross-disciplinary physics: materials science; rheology ; Electronics ; Exact sciences and technology ; Germanium ; Germanium MOSFET ; Germanium passivation ; Low temperature CVD ; Materials science ; Methods of deposition of films and coatings; film growth and epitaxy ; Microelectronic fabrication (materials and surfaces technology) ; Monolayers ; Passivation ; Physics ; Precursors ; Segregations ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Si precursors ; Silicon ; Silicon substrates ; Transistors ; Trisilane ; Ultrathin Si growth on germanium</subject><ispartof>Solid-state electronics, 2011-06, Vol.60 (1), p.116-121</ispartof><rights>2011 Elsevier Ltd</rights><rights>2015 INIST-CNRS</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c359t-7face02b2d86a6c8e0ab1d20094f6ed2f0cfbd92ad0585a8aef8c07bcec0ea853</citedby><cites>FETCH-LOGICAL-c359t-7face02b2d86a6c8e0ab1d20094f6ed2f0cfbd92ad0585a8aef8c07bcec0ea853</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://www.sciencedirect.com/science/article/pii/S0038110111000785$$EHTML$$P50$$Gelsevier$$H</linktohtml><link.rule.ids>309,310,314,776,780,785,786,3537,23909,23910,25118,27901,27902,65306</link.rule.ids><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=24242845$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Vincent, B.</creatorcontrib><creatorcontrib>Loo, R.</creatorcontrib><creatorcontrib>Vandervorst, W.</creatorcontrib><creatorcontrib>Delmotte, J.</creatorcontrib><creatorcontrib>Douhard, B.</creatorcontrib><creatorcontrib>Valev, V.K.</creatorcontrib><creatorcontrib>Vanbel, M.</creatorcontrib><creatorcontrib>Verbiest, T.</creatorcontrib><creatorcontrib>Rip, J.</creatorcontrib><creatorcontrib>Brijs, B.</creatorcontrib><creatorcontrib>Conard, T.</creatorcontrib><creatorcontrib>Claypool, C.</creatorcontrib><creatorcontrib>Takeuchi, S.</creatorcontrib><creatorcontrib>Zaima, S.</creatorcontrib><creatorcontrib>Mitard, J.</creatorcontrib><creatorcontrib>De Jaeger, B.</creatorcontrib><creatorcontrib>Dekoster, J.</creatorcontrib><creatorcontrib>Caymax, M.</creatorcontrib><title>Si passivation for Ge pMOSFETs: Impact of Si cap growth conditions</title><title>Solid-state electronics</title><description>► Impact of Si cap Ge passivation pn Ge pMOSFETs performances. ► Impact of RPCVD Si growth process conditions on Si crystallinity and Ge segregation. ► Offers the best route for Ge passivation.
Ultra thin Si cap growth by Reduced Pressure Chemical Vapor Deposition on relaxed Ge substrates is detailed in this paper for Ge pMOSFET (Metal Oxide Semiconductor Field Effect Transistors) passivation purposes. A cross calibration of different measurement techniques is first proposed to perfectly monitor Si monolayers thickness deposited on Ge substrates. Different characteristics, impacting Ge pMOSFETs device performances, are next detailed for various Si cap growth processes using different Si precursors: DiChloroSilane (DCS), silane and trisilane. The critical Si thickness of plastic relaxation has been determined at 12 monolayers. Presence of point defects has been identified for very low growth temperature as 350
°C. Ge–Si intermixing, caused by a Ge segregation mechanism, is strongly reduced by the use of trisilane as Si precursor at low temperatures.</description><subject>Applied sciences</subject><subject>Chemical vapor deposition (including plasma-enhanced cvd, mocvd, etc.)</subject><subject>Cross-disciplinary physics: materials science; rheology</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Germanium</subject><subject>Germanium MOSFET</subject><subject>Germanium passivation</subject><subject>Low temperature CVD</subject><subject>Materials science</subject><subject>Methods of deposition of films and coatings; film growth and epitaxy</subject><subject>Microelectronic fabrication (materials and surfaces technology)</subject><subject>Monolayers</subject><subject>Passivation</subject><subject>Physics</subject><subject>Precursors</subject><subject>Segregations</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Si precursors</subject><subject>Silicon</subject><subject>Silicon substrates</subject><subject>Transistors</subject><subject>Trisilane</subject><subject>Ultrathin Si growth on germanium</subject><issn>0038-1101</issn><issn>1879-2405</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2011</creationdate><recordtype>article</recordtype><recordid>eNp9kEFPGzEQha2KSg0pP4CbLxWnTcfO7sZbTgW1FImKA-VsTWbH4ChZbz0LiH9fR0EcKz1pLt97M_OUOjWwMGDar5uFCC8sGLOAorr7oGbGrbrK1tAcqRnA0lWmoJ_UscgGAGxrYKYu7qIeUSQ-4xTToEPK-or1-Pv27uePP_JNX-9GpEmnoAtJOOqHnF6mR01p6OPeIp_Vx4Bb4ZO3OVf3xXr5q7q5vbq-_H5T0bLppmoVkBjs2vauxZYcA65NbwG6OrTc2wAU1n1nsYfGNeiQgyNYrYkJGF2znKuzQ-6Y098nlsnvohBvtzhwehLvXFfbuu6WhTQHknISyRz8mOMO86s34Pd1-Y0vdfl9XR6KimmuvryloxBuQ8aBorwbbYm2rt5fcX7guLz6HDl7ocgDcR8z0-T7FP-z5R9dx3-W</recordid><startdate>20110601</startdate><enddate>20110601</enddate><creator>Vincent, B.</creator><creator>Loo, R.</creator><creator>Vandervorst, W.</creator><creator>Delmotte, J.</creator><creator>Douhard, B.</creator><creator>Valev, V.K.</creator><creator>Vanbel, M.</creator><creator>Verbiest, T.</creator><creator>Rip, J.</creator><creator>Brijs, B.</creator><creator>Conard, T.</creator><creator>Claypool, C.</creator><creator>Takeuchi, S.</creator><creator>Zaima, S.</creator><creator>Mitard, J.</creator><creator>De Jaeger, B.</creator><creator>Dekoster, J.</creator><creator>Caymax, M.</creator><general>Elsevier Ltd</general><general>Elsevier</general><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>7U5</scope><scope>8FD</scope><scope>H8D</scope><scope>L7M</scope></search><sort><creationdate>20110601</creationdate><title>Si passivation for Ge pMOSFETs: Impact of Si cap growth conditions</title><author>Vincent, B. ; Loo, R. ; Vandervorst, W. ; Delmotte, J. ; Douhard, B. ; Valev, V.K. ; Vanbel, M. ; Verbiest, T. ; Rip, J. ; Brijs, B. ; Conard, T. ; Claypool, C. ; Takeuchi, S. ; Zaima, S. ; Mitard, J. ; De Jaeger, B. ; Dekoster, J. ; Caymax, M.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c359t-7face02b2d86a6c8e0ab1d20094f6ed2f0cfbd92ad0585a8aef8c07bcec0ea853</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2011</creationdate><topic>Applied sciences</topic><topic>Chemical vapor deposition (including plasma-enhanced cvd, mocvd, etc.)</topic><topic>Cross-disciplinary physics: materials science; rheology</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Germanium</topic><topic>Germanium MOSFET</topic><topic>Germanium passivation</topic><topic>Low temperature CVD</topic><topic>Materials science</topic><topic>Methods of deposition of films and coatings; film growth and epitaxy</topic><topic>Microelectronic fabrication (materials and surfaces technology)</topic><topic>Monolayers</topic><topic>Passivation</topic><topic>Physics</topic><topic>Precursors</topic><topic>Segregations</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Si precursors</topic><topic>Silicon</topic><topic>Silicon substrates</topic><topic>Transistors</topic><topic>Trisilane</topic><topic>Ultrathin Si growth on germanium</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Vincent, B.</creatorcontrib><creatorcontrib>Loo, R.</creatorcontrib><creatorcontrib>Vandervorst, W.</creatorcontrib><creatorcontrib>Delmotte, J.</creatorcontrib><creatorcontrib>Douhard, B.</creatorcontrib><creatorcontrib>Valev, V.K.</creatorcontrib><creatorcontrib>Vanbel, M.</creatorcontrib><creatorcontrib>Verbiest, T.</creatorcontrib><creatorcontrib>Rip, J.</creatorcontrib><creatorcontrib>Brijs, B.</creatorcontrib><creatorcontrib>Conard, T.</creatorcontrib><creatorcontrib>Claypool, C.</creatorcontrib><creatorcontrib>Takeuchi, S.</creatorcontrib><creatorcontrib>Zaima, S.</creatorcontrib><creatorcontrib>Mitard, J.</creatorcontrib><creatorcontrib>De Jaeger, B.</creatorcontrib><creatorcontrib>Dekoster, J.</creatorcontrib><creatorcontrib>Caymax, M.</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>Technology Research Database</collection><collection>Aerospace Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>Solid-state electronics</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Vincent, B.</au><au>Loo, R.</au><au>Vandervorst, W.</au><au>Delmotte, J.</au><au>Douhard, B.</au><au>Valev, V.K.</au><au>Vanbel, M.</au><au>Verbiest, T.</au><au>Rip, J.</au><au>Brijs, B.</au><au>Conard, T.</au><au>Claypool, C.</au><au>Takeuchi, S.</au><au>Zaima, S.</au><au>Mitard, J.</au><au>De Jaeger, B.</au><au>Dekoster, J.</au><au>Caymax, M.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Si passivation for Ge pMOSFETs: Impact of Si cap growth conditions</atitle><jtitle>Solid-state electronics</jtitle><date>2011-06-01</date><risdate>2011</risdate><volume>60</volume><issue>1</issue><spage>116</spage><epage>121</epage><pages>116-121</pages><issn>0038-1101</issn><eissn>1879-2405</eissn><abstract>► Impact of Si cap Ge passivation pn Ge pMOSFETs performances. ► Impact of RPCVD Si growth process conditions on Si crystallinity and Ge segregation. ► Offers the best route for Ge passivation.
Ultra thin Si cap growth by Reduced Pressure Chemical Vapor Deposition on relaxed Ge substrates is detailed in this paper for Ge pMOSFET (Metal Oxide Semiconductor Field Effect Transistors) passivation purposes. A cross calibration of different measurement techniques is first proposed to perfectly monitor Si monolayers thickness deposited on Ge substrates. Different characteristics, impacting Ge pMOSFETs device performances, are next detailed for various Si cap growth processes using different Si precursors: DiChloroSilane (DCS), silane and trisilane. The critical Si thickness of plastic relaxation has been determined at 12 monolayers. Presence of point defects has been identified for very low growth temperature as 350
°C. Ge–Si intermixing, caused by a Ge segregation mechanism, is strongly reduced by the use of trisilane as Si precursor at low temperatures.</abstract><cop>Kidlington</cop><pub>Elsevier Ltd</pub><doi>10.1016/j.sse.2011.01.049</doi><tpages>6</tpages></addata></record> |
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| subjects | Applied sciences Chemical vapor deposition (including plasma-enhanced cvd, mocvd, etc.) Cross-disciplinary physics: materials science rheology Electronics Exact sciences and technology Germanium Germanium MOSFET Germanium passivation Low temperature CVD Materials science Methods of deposition of films and coatings film growth and epitaxy Microelectronic fabrication (materials and surfaces technology) Monolayers Passivation Physics Precursors Segregations Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Si precursors Silicon Silicon substrates Transistors Trisilane Ultrathin Si growth on germanium |
| title | Si passivation for Ge pMOSFETs: Impact of Si cap growth conditions |
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