Comparison of low-temperature electrical characteristics of gate-all-around nanowire FETs, Fin FETs and fully-depleted SOI FETs
Low-temperature electrical characteristics of n-type gate-all-around vertically-stacked silicon nanowire (SNW) field-effect transistors (FETs) with high- k/metal gate have been investigated and are compared to those with Fin and fully-depleted silicon-on-insulator (FD SOI) FETs. In particular, the e...
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| Veröffentlicht in: | Microelectronics and reliability 2011-05, Vol.51 (5), p.885-888 |
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| container_title | Microelectronics and reliability |
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| creator | Tachi, Kiichi Barraud, Sylvain Kakushima, Kuniyuki Iwai, Hiroshi Cristoloveanu, Sorin Ernst, Thomas |
| description | Low-temperature electrical characteristics of
n-type gate-all-around vertically-stacked silicon nanowire (SNW) field-effect transistors (FETs) with high-
k/metal gate have been investigated and are compared to those with Fin and fully-depleted silicon-on-insulator (FD SOI) FETs. In particular, the effective electron mobilities behaviors are discussed. Nanowires with a rectangular cross section of 15
nm in width and 19
nm in height have shown a strongly degraded mobility as compared to those with Fin and FD SOI FETs. Low-temperature measurements have revealed that the mobility degradation is due to higher surface-roughness limited mobility. On the other hand, no significant difference in the interface trap densities among the kinds of FETs measured in the study have been observed from the temperature dependence in the subthreshold slope. |
| doi_str_mv | 10.1016/j.microrel.2011.01.004 |
| format | Article |
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n-type gate-all-around vertically-stacked silicon nanowire (SNW) field-effect transistors (FETs) with high-
k/metal gate have been investigated and are compared to those with Fin and fully-depleted silicon-on-insulator (FD SOI) FETs. In particular, the effective electron mobilities behaviors are discussed. Nanowires with a rectangular cross section of 15
nm in width and 19
nm in height have shown a strongly degraded mobility as compared to those with Fin and FD SOI FETs. Low-temperature measurements have revealed that the mobility degradation is due to higher surface-roughness limited mobility. On the other hand, no significant difference in the interface trap densities among the kinds of FETs measured in the study have been observed from the temperature dependence in the subthreshold slope.</description><identifier>ISSN: 0026-2714</identifier><identifier>EISSN: 1872-941X</identifier><identifier>DOI: 10.1016/j.microrel.2011.01.004</identifier><identifier>CODEN: MCRLAS</identifier><language>eng</language><publisher>Kidlington: Elsevier Ltd</publisher><subject>Applied sciences ; Cross sections ; Cross-disciplinary physics: materials science; rheology ; Degradation ; Density ; Electron mobility ; Electronics ; Exact sciences and technology ; Materials science ; Nanocomposites ; Nanomaterials ; Nanoscale materials and structures: fabrication and characterization ; Nanostructure ; Nanowires ; Physics ; Quantum wires ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Temperature dependence ; Transistors</subject><ispartof>Microelectronics and reliability, 2011-05, Vol.51 (5), p.885-888</ispartof><rights>2011 Elsevier Ltd</rights><rights>2015 INIST-CNRS</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c451t-3fadbfd9dab3f3b53a1a57bed329eb60c389adb8cfe42e0a0042ac492624a2843</citedby><cites>FETCH-LOGICAL-c451t-3fadbfd9dab3f3b53a1a57bed329eb60c389adb8cfe42e0a0042ac492624a2843</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://www.sciencedirect.com/science/article/pii/S0026271411000060$$EHTML$$P50$$Gelsevier$$H</linktohtml><link.rule.ids>314,776,780,3537,27901,27902,65534</link.rule.ids><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=24076598$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Tachi, Kiichi</creatorcontrib><creatorcontrib>Barraud, Sylvain</creatorcontrib><creatorcontrib>Kakushima, Kuniyuki</creatorcontrib><creatorcontrib>Iwai, Hiroshi</creatorcontrib><creatorcontrib>Cristoloveanu, Sorin</creatorcontrib><creatorcontrib>Ernst, Thomas</creatorcontrib><title>Comparison of low-temperature electrical characteristics of gate-all-around nanowire FETs, Fin FETs and fully-depleted SOI FETs</title><title>Microelectronics and reliability</title><description>Low-temperature electrical characteristics of
n-type gate-all-around vertically-stacked silicon nanowire (SNW) field-effect transistors (FETs) with high-
k/metal gate have been investigated and are compared to those with Fin and fully-depleted silicon-on-insulator (FD SOI) FETs. In particular, the effective electron mobilities behaviors are discussed. Nanowires with a rectangular cross section of 15
nm in width and 19
nm in height have shown a strongly degraded mobility as compared to those with Fin and FD SOI FETs. Low-temperature measurements have revealed that the mobility degradation is due to higher surface-roughness limited mobility. On the other hand, no significant difference in the interface trap densities among the kinds of FETs measured in the study have been observed from the temperature dependence in the subthreshold slope.</description><subject>Applied sciences</subject><subject>Cross sections</subject><subject>Cross-disciplinary physics: materials science; rheology</subject><subject>Degradation</subject><subject>Density</subject><subject>Electron mobility</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Materials science</subject><subject>Nanocomposites</subject><subject>Nanomaterials</subject><subject>Nanoscale materials and structures: fabrication and characterization</subject><subject>Nanostructure</subject><subject>Nanowires</subject><subject>Physics</subject><subject>Quantum wires</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. 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Microelectronics. Optoelectronics. Solid state devices</topic><topic>Temperature dependence</topic><topic>Transistors</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Tachi, Kiichi</creatorcontrib><creatorcontrib>Barraud, Sylvain</creatorcontrib><creatorcontrib>Kakushima, Kuniyuki</creatorcontrib><creatorcontrib>Iwai, Hiroshi</creatorcontrib><creatorcontrib>Cristoloveanu, Sorin</creatorcontrib><creatorcontrib>Ernst, Thomas</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>Microelectronics and reliability</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Tachi, Kiichi</au><au>Barraud, Sylvain</au><au>Kakushima, Kuniyuki</au><au>Iwai, Hiroshi</au><au>Cristoloveanu, Sorin</au><au>Ernst, Thomas</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Comparison of low-temperature electrical characteristics of gate-all-around nanowire FETs, Fin FETs and fully-depleted SOI FETs</atitle><jtitle>Microelectronics and reliability</jtitle><date>2011-05-01</date><risdate>2011</risdate><volume>51</volume><issue>5</issue><spage>885</spage><epage>888</epage><pages>885-888</pages><issn>0026-2714</issn><eissn>1872-941X</eissn><coden>MCRLAS</coden><abstract>Low-temperature electrical characteristics of
n-type gate-all-around vertically-stacked silicon nanowire (SNW) field-effect transistors (FETs) with high-
k/metal gate have been investigated and are compared to those with Fin and fully-depleted silicon-on-insulator (FD SOI) FETs. In particular, the effective electron mobilities behaviors are discussed. Nanowires with a rectangular cross section of 15
nm in width and 19
nm in height have shown a strongly degraded mobility as compared to those with Fin and FD SOI FETs. Low-temperature measurements have revealed that the mobility degradation is due to higher surface-roughness limited mobility. On the other hand, no significant difference in the interface trap densities among the kinds of FETs measured in the study have been observed from the temperature dependence in the subthreshold slope.</abstract><cop>Kidlington</cop><pub>Elsevier Ltd</pub><doi>10.1016/j.microrel.2011.01.004</doi><tpages>4</tpages></addata></record> |
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| subjects | Applied sciences Cross sections Cross-disciplinary physics: materials science rheology Degradation Density Electron mobility Electronics Exact sciences and technology Materials science Nanocomposites Nanomaterials Nanoscale materials and structures: fabrication and characterization Nanostructure Nanowires Physics Quantum wires Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Temperature dependence Transistors |
| title | Comparison of low-temperature electrical characteristics of gate-all-around nanowire FETs, Fin FETs and fully-depleted SOI FETs |
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