Efficient modulo 2 n ±1 squarers
Modulo 2 n ±1 squarers are useful components for designing special purpose digital signal processors that internally use a residue number system and for implementing the modulo exponentiators and multiplicative inverses required in cryptographic algorithms. In this paper we propose, in a unified way...
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| Veröffentlicht in: | Integration (Amsterdam) 2011-06, Vol.44 (3), p.163-174 |
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| container_title | Integration (Amsterdam) |
| container_volume | 44 |
| creator | Bakalis, D. Vergos, H.T. Spyrou, A. |
| description | Modulo 2
n
±1 squarers are useful components for designing special purpose digital signal processors that internally use a residue number system and for implementing the modulo exponentiators and multiplicative inverses required in cryptographic algorithms. In this paper we propose, in a unified way, architectures for their design that are based on the radix-4 modified Booth encoding. For the modulo 2
n
+1 case, both the normal and the diminished-one representations are considered. Experimental results show that the proposed squarers offer significant savings in the implementation area over previous proposals that can reach up to 38% for sufficiently large operand widths, while in many cases a small improvement in execution delay can also be achieved. |
| doi_str_mv | 10.1016/j.vlsi.2011.03.006 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_elsev</sourceid><recordid>TN_cdi_proquest_miscellaneous_880658051</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><els_id>S0167926011000319</els_id><sourcerecordid>880658051</sourcerecordid><originalsourceid>FETCH-LOGICAL-e851-f21d5a57a1a4efaf644409ca8c4acce7108f0ff472bcb3bc78ce0e0d8bd0abe3</originalsourceid><addsrcrecordid>eNotkMFKxDAURYMoWEd_wFVduWp9L02aDLiRYUaFARe6D2n6Aimd1mna-S9_wS-zZVzdzeFyOIzdI-QIWD41-amNIeeAmEORA5QXLEGteKYk55csmSGVrXkJ1-wmxgYAUCiZsIet98EF6sb00NdT26c87dLfH0zjcbIDDfGWXXnbRrr73xX73G2_Nm_Z_uP1ffOyz0hLzDzHWlqpLFpB3vpSCAFrZ7UT1jlSCNqD90LxylVF5ZR2BAS1rmqwFRUr9nh-_R7640RxNIcQHbWt7aifotEaSqlB4kw-n0maZU6BBhMXf0d1GMiNpu6DQTBLFtOYJYtZshgozJyl-AMVklfk</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>880658051</pqid></control><display><type>article</type><title>Efficient modulo 2 n ±1 squarers</title><source>Elsevier ScienceDirect Journals Complete</source><creator>Bakalis, D. ; Vergos, H.T. ; Spyrou, A.</creator><creatorcontrib>Bakalis, D. ; Vergos, H.T. ; Spyrou, A.</creatorcontrib><description>Modulo 2
n
±1 squarers are useful components for designing special purpose digital signal processors that internally use a residue number system and for implementing the modulo exponentiators and multiplicative inverses required in cryptographic algorithms. In this paper we propose, in a unified way, architectures for their design that are based on the radix-4 modified Booth encoding. For the modulo 2
n
+1 case, both the normal and the diminished-one representations are considered. Experimental results show that the proposed squarers offer significant savings in the implementation area over previous proposals that can reach up to 38% for sufficiently large operand widths, while in many cases a small improvement in execution delay can also be achieved.</description><identifier>ISSN: 0167-9260</identifier><identifier>EISSN: 1872-7522</identifier><identifier>DOI: 10.1016/j.vlsi.2011.03.006</identifier><language>eng</language><publisher>Elsevier B.V</publisher><subject>Booth encoding ; Booths ; Computer arithmetic ; Cryptography ; Delay ; Design engineering ; Digital ; Modulo arithmetic ; Processors ; Representations ; Residue number system ; Residue number systems ; Squarers</subject><ispartof>Integration (Amsterdam), 2011-06, Vol.44 (3), p.163-174</ispartof><rights>2011 Elsevier B.V.</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://dx.doi.org/10.1016/j.vlsi.2011.03.006$$EHTML$$P50$$Gelsevier$$H</linktohtml><link.rule.ids>314,780,784,3550,27924,27925,45995</link.rule.ids></links><search><creatorcontrib>Bakalis, D.</creatorcontrib><creatorcontrib>Vergos, H.T.</creatorcontrib><creatorcontrib>Spyrou, A.</creatorcontrib><title>Efficient modulo 2 n ±1 squarers</title><title>Integration (Amsterdam)</title><description>Modulo 2
n
±1 squarers are useful components for designing special purpose digital signal processors that internally use a residue number system and for implementing the modulo exponentiators and multiplicative inverses required in cryptographic algorithms. In this paper we propose, in a unified way, architectures for their design that are based on the radix-4 modified Booth encoding. For the modulo 2
n
+1 case, both the normal and the diminished-one representations are considered. Experimental results show that the proposed squarers offer significant savings in the implementation area over previous proposals that can reach up to 38% for sufficiently large operand widths, while in many cases a small improvement in execution delay can also be achieved.</description><subject>Booth encoding</subject><subject>Booths</subject><subject>Computer arithmetic</subject><subject>Cryptography</subject><subject>Delay</subject><subject>Design engineering</subject><subject>Digital</subject><subject>Modulo arithmetic</subject><subject>Processors</subject><subject>Representations</subject><subject>Residue number system</subject><subject>Residue number systems</subject><subject>Squarers</subject><issn>0167-9260</issn><issn>1872-7522</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2011</creationdate><recordtype>article</recordtype><recordid>eNotkMFKxDAURYMoWEd_wFVduWp9L02aDLiRYUaFARe6D2n6Aimd1mna-S9_wS-zZVzdzeFyOIzdI-QIWD41-amNIeeAmEORA5QXLEGteKYk55csmSGVrXkJ1-wmxgYAUCiZsIet98EF6sb00NdT26c87dLfH0zjcbIDDfGWXXnbRrr73xX73G2_Nm_Z_uP1ffOyz0hLzDzHWlqpLFpB3vpSCAFrZ7UT1jlSCNqD90LxylVF5ZR2BAS1rmqwFRUr9nh-_R7640RxNIcQHbWt7aifotEaSqlB4kw-n0maZU6BBhMXf0d1GMiNpu6DQTBLFtOYJYtZshgozJyl-AMVklfk</recordid><startdate>20110601</startdate><enddate>20110601</enddate><creator>Bakalis, D.</creator><creator>Vergos, H.T.</creator><creator>Spyrou, A.</creator><general>Elsevier B.V</general><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope></search><sort><creationdate>20110601</creationdate><title>Efficient modulo 2 n ±1 squarers</title><author>Bakalis, D. ; Vergos, H.T. ; Spyrou, A.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-e851-f21d5a57a1a4efaf644409ca8c4acce7108f0ff472bcb3bc78ce0e0d8bd0abe3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2011</creationdate><topic>Booth encoding</topic><topic>Booths</topic><topic>Computer arithmetic</topic><topic>Cryptography</topic><topic>Delay</topic><topic>Design engineering</topic><topic>Digital</topic><topic>Modulo arithmetic</topic><topic>Processors</topic><topic>Representations</topic><topic>Residue number system</topic><topic>Residue number systems</topic><topic>Squarers</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Bakalis, D.</creatorcontrib><creatorcontrib>Vergos, H.T.</creatorcontrib><creatorcontrib>Spyrou, A.</creatorcontrib><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>Integration (Amsterdam)</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Bakalis, D.</au><au>Vergos, H.T.</au><au>Spyrou, A.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Efficient modulo 2 n ±1 squarers</atitle><jtitle>Integration (Amsterdam)</jtitle><date>2011-06-01</date><risdate>2011</risdate><volume>44</volume><issue>3</issue><spage>163</spage><epage>174</epage><pages>163-174</pages><issn>0167-9260</issn><eissn>1872-7522</eissn><abstract>Modulo 2
n
±1 squarers are useful components for designing special purpose digital signal processors that internally use a residue number system and for implementing the modulo exponentiators and multiplicative inverses required in cryptographic algorithms. In this paper we propose, in a unified way, architectures for their design that are based on the radix-4 modified Booth encoding. For the modulo 2
n
+1 case, both the normal and the diminished-one representations are considered. Experimental results show that the proposed squarers offer significant savings in the implementation area over previous proposals that can reach up to 38% for sufficiently large operand widths, while in many cases a small improvement in execution delay can also be achieved.</abstract><pub>Elsevier B.V</pub><doi>10.1016/j.vlsi.2011.03.006</doi><tpages>12</tpages></addata></record> |
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| ispartof | Integration (Amsterdam), 2011-06, Vol.44 (3), p.163-174 |
| issn | 0167-9260 1872-7522 |
| language | eng |
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| source | Elsevier ScienceDirect Journals Complete |
| subjects | Booth encoding Booths Computer arithmetic Cryptography Delay Design engineering Digital Modulo arithmetic Processors Representations Residue number system Residue number systems Squarers |
| title | Efficient modulo 2 n ±1 squarers |
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