A 12-Bit Ratio-Independent Algorithmic A/D Converter for a Capacitive Sensor Interface

This paper describes a ratio-independent algorithmic analog-digital (A/D) converter architecture that is insensitive to capacitance ratio, amplifier offset voltage, amplifier input parasitics, and flicker noise. It requires only one differential amplifier, a dynamic latch, six capacitors, 36 switche...

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Veröffentlicht in:	IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2008-04, Vol.55 (3), p.730-740
Hauptverfasser:	Jarvinen, J.A.M., Saukoski, M., Halonen, K.A.I.
Format:	Artikel
Sprache:	eng
Schlagworte:	1f noise Accelerometer algorithmic analog-digital (A/D) converter Algorithms Amplifiers Analog-digital conversion Capacitance Capacitive sensors Capacitors CMOS logic circuits Converters Differential amplifiers Dynamical systems Dynamics Logic low power Parasitic capacitance Power dissipation ratio independent sensor Switches Voltage
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