A Hierarchical Framework for Design Space Exploration and Optimization of TTP-Based Distributed Embedded Systems
Time-triggered protocol (TTP) is a time-division multiple access (TDMA)-based bus protocol designed for use in safety-critical avionics and automotive distributed embedded systems. Design space exploration (DSE) for TTP-based distributed embedded system involves searching through a vast design space...
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| Veröffentlicht in: | IEEE transactions on industrial informatics 2008-11, Vol.4 (4), p.237-249 |
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| creator | He, Xiuqiang Yuan, Mingxuan Gu, Zonghua |
| description | Time-triggered protocol (TTP) is a time-division multiple access (TDMA)-based bus protocol designed for use in safety-critical avionics and automotive distributed embedded systems. Design space exploration (DSE) for TTP-based distributed embedded system involves searching through a vast design space of possible task-to-CPU mappings, task/message schedules and bus access configurations to achieve certain design objectives. In this paper, we present an efficient two-level hierarchical DSE framework for TTP-based distributed embedded systems, with the objective of minimizing the total bus utilization while meeting an end-to-end deadline constraint. Logic-based Benders decomposition (LBBD) is used to divide the problem into a master problem of mapping tasks to CPU nodes to minimize the total bus utilization, solved with a satisfiability modulo theories (SMT) solver, and a subproblem of finding a feasible solution of bus access configuration and task/message schedule under an end-to-end deadline constraint for a given task-to-CPU mapping, solved with a constraint programming (CP) solver. Performance evaluation results show that our approach is scalable to problems with realistic size. |
| doi_str_mv | 10.1109/TII.2008.2010519 |
| format | Article |
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Design space exploration (DSE) for TTP-based distributed embedded system involves searching through a vast design space of possible task-to-CPU mappings, task/message schedules and bus access configurations to achieve certain design objectives. In this paper, we present an efficient two-level hierarchical DSE framework for TTP-based distributed embedded systems, with the objective of minimizing the total bus utilization while meeting an end-to-end deadline constraint. Logic-based Benders decomposition (LBBD) is used to divide the problem into a master problem of mapping tasks to CPU nodes to minimize the total bus utilization, solved with a satisfiability modulo theories (SMT) solver, and a subproblem of finding a feasible solution of bus access configuration and task/message schedule under an end-to-end deadline constraint for a given task-to-CPU mapping, solved with a constraint programming (CP) solver. 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| ispartof | IEEE transactions on industrial informatics, 2008-11, Vol.4 (4), p.237-249 |
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| source | IEEE Electronic Library (IEL) |
| subjects | Access protocols Aerospace electronics Automotive engineering Benders decomposition Buses (vehicles) constraint programming Constraint theory Control systems Design engineering Design optimization Embedded system Embedded systems Job shop scheduling Mapping Runtime satisfiability modulo theories Schedules Solvers Space exploration Studies Tasks time-triggered protocol Utilization |
| title | A Hierarchical Framework for Design Space Exploration and Optimization of TTP-Based Distributed Embedded Systems |
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