Reducing Ground-Bounce Noise and Stabilizing the Data-Retention Voltage of Power-Gating Structures
Power gating is one of the most effective techniques in reducing leakage power, which increases exponentially with device scaling. However, large ground bounces during abrupt changes of power mode may cause unwanted transitions in neighboring circuits, which should still be operating normally. We an...
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| Veröffentlicht in: | IEEE transactions on electron devices 2008-01, Vol.55 (1), p.197-205 |
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| container_title | IEEE transactions on electron devices |
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| creator | Suhwan Kim Chang Jun Choi Deog-Kyoon Jeong Kosonocky, S.V. Sung Bae Park |
| description | Power gating is one of the most effective techniques in reducing leakage power, which increases exponentially with device scaling. However, large ground bounces during abrupt changes of power mode may cause unwanted transitions in neighboring circuits, which should still be operating normally. We analyzed this ground-bounce noise and reduced it with novel power-gating structures that utilize holistic integrated device-circuit-architecture approaches. We control the amount of charge in the intermediate nodes of the circuit that passes through the sleep transistors during the wake-up transition and stabilize the minimum virtual power supply voltage required for data retention. These techniques have been proven in silicon using 65-nm bulk CMOS technology. |
| doi_str_mv | 10.1109/TED.2007.911067 |
| format | Article |
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| subjects | Circuits CMOS CMOS integrated circuits CMOS technology CMOS technology scaling device/circuit codesign Devices Electric potential Gating and risering ground-bounce noise Grounds Logic gates Noise power-gating technique Rails Switching circuits Transistors Voltage |
| title | Reducing Ground-Bounce Noise and Stabilizing the Data-Retention Voltage of Power-Gating Structures |
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