Simple and Accurate Models for Capacitance Considering Floating Metal Fill Insertion
In this paper, we analyze and model the impact of floating dummy fill on the signal capacitance considering various parameters including signal dimensions, dummy shape and dimensions. Intra-layer dummy has its greatest impact on coupling capacitance while inter-layer dummy has larger impact on the g...
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| Veröffentlicht in: | IEEE transactions on very large scale integration (VLSI) systems 2009-08, Vol.17 (8), p.1166-1170 |
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| container_title | IEEE transactions on very large scale integration (VLSI) systems |
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| creator | Youngmin Kim Petranovic, D. Sylvester, D. |
| description | In this paper, we analyze and model the impact of floating dummy fill on the signal capacitance considering various parameters including signal dimensions, dummy shape and dimensions. Intra-layer dummy has its greatest impact on coupling capacitance while inter-layer dummy has larger impact on the ground capacitance component. Based on this analysis, we propose simple capacitance models (Cc for intra-layer dummy and Cg for inter-layer dummy). To consider realistic cases with both signals and metal fill in adjacent layers, we apply a weighting function approach to the Cg model. We verify this model using benchmark circuits and find that total net capacitance with floating fill can be extracted within ~1% of field solver results on average with total extraction runtime reductions of up to 40%. When evaluating the incremental capacitance due to fill alone, average error of the models range from 2%-15% across benchmarks and fill-related runtime overhead is reduced by 60%-88%. |
| doi_str_mv | 10.1109/TVLSI.2009.2020392 |
| format | Article |
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Intra-layer dummy has its greatest impact on coupling capacitance while inter-layer dummy has larger impact on the ground capacitance component. Based on this analysis, we propose simple capacitance models (Cc for intra-layer dummy and Cg for inter-layer dummy). To consider realistic cases with both signals and metal fill in adjacent layers, we apply a weighting function approach to the Cg model. We verify this model using benchmark circuits and find that total net capacitance with floating fill can be extracted within ~1% of field solver results on average with total extraction runtime reductions of up to 40%. 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Intra-layer dummy has its greatest impact on coupling capacitance while inter-layer dummy has larger impact on the ground capacitance component. Based on this analysis, we propose simple capacitance models (Cc for intra-layer dummy and Cg for inter-layer dummy). To consider realistic cases with both signals and metal fill in adjacent layers, we apply a weighting function approach to the Cg model. We verify this model using benchmark circuits and find that total net capacitance with floating fill can be extracted within ~1% of field solver results on average with total extraction runtime reductions of up to 40%. When evaluating the incremental capacitance due to fill alone, average error of the models range from 2%-15% across benchmarks and fill-related runtime overhead is reduced by 60%-88%.</description><subject>Applied sciences</subject><subject>Benchmarking</subject><subject>Capacitance</subject><subject>Circuits</subject><subject>Crosstalk</subject><subject>Degradation</subject><subject>Delay</subject><subject>design</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Dummies</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Grounds</subject><subject>Integrated circuit interconnections</subject><subject>Integrated circuits</subject><subject>integrated circuits (ICs)</subject><subject>inter connects</subject><subject>Parasitic capacitance</subject><subject>Runtime</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. 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Solid state devices</topic><topic>Shape</topic><topic>Signal analysis</topic><topic>Silicon</topic><topic>Solvers</topic><topic>Very large scale integration</topic><topic>Weighting functions</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Youngmin Kim</creatorcontrib><creatorcontrib>Petranovic, D.</creatorcontrib><creatorcontrib>Sylvester, D.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Youngmin Kim</au><au>Petranovic, D.</au><au>Sylvester, D.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Simple and Accurate Models for Capacitance Considering Floating Metal Fill Insertion</atitle><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle><stitle>TVLSI</stitle><date>2009-08-01</date><risdate>2009</risdate><volume>17</volume><issue>8</issue><spage>1166</spage><epage>1170</epage><pages>1166-1170</pages><issn>1063-8210</issn><eissn>1557-9999</eissn><coden>IEVSE9</coden><abstract>In this paper, we analyze and model the impact of floating dummy fill on the signal capacitance considering various parameters including signal dimensions, dummy shape and dimensions. Intra-layer dummy has its greatest impact on coupling capacitance while inter-layer dummy has larger impact on the ground capacitance component. Based on this analysis, we propose simple capacitance models (Cc for intra-layer dummy and Cg for inter-layer dummy). To consider realistic cases with both signals and metal fill in adjacent layers, we apply a weighting function approach to the Cg model. We verify this model using benchmark circuits and find that total net capacitance with floating fill can be extracted within ~1% of field solver results on average with total extraction runtime reductions of up to 40%. When evaluating the incremental capacitance due to fill alone, average error of the models range from 2%-15% across benchmarks and fill-related runtime overhead is reduced by 60%-88%.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/TVLSI.2009.2020392</doi><tpages>5</tpages></addata></record> |
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| subjects | Applied sciences Benchmarking Capacitance Circuits Crosstalk Degradation Delay design Design. Technologies. Operation analysis. Testing Dummies Electronics Exact sciences and technology Grounds Integrated circuit interconnections Integrated circuits integrated circuits (ICs) inter connects Parasitic capacitance Runtime Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Shape Signal analysis Silicon Solvers Very large scale integration Weighting functions |
| title | Simple and Accurate Models for Capacitance Considering Floating Metal Fill Insertion |
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