A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface

This paper describes a bidirectional, differential, 16 Gb/s per link memory interface that includes a Controller and an emulated DRAM physical interface (PHY) designed in 65 nm CMOS. To achieve high data rate, the interface employs the following technology ingredients: asymmetric equalization, asymm...

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Veröffentlicht in:	IEEE journal of solid-state circuits 2009-04, Vol.44 (4), p.1235-1247
Hauptverfasser:	Haechang Lee, Kun-Yung Ken Chang, Jung-Hoon Chun, Ting Wu, Frans, Y., Leibowitz, B., Nhat Nguyen, Chin, T.J., Kaviani, K., Shen, J., Xudong Shi, Beyene, W.T., Li, S., Navid, R., Aleksic, M., Lee, F.S., Quan, F., Zerbe, J., Perego, R., Assaderaghi, F.
Format:	Artikel
Sprache:	eng
Schlagworte:	Applied sciences Asymmetry Bandwidth Bidirectional Calibration Channels Circuit properties Circuits of signal characteristics conditioning (including delay circuits) CMOS memory integrated circuits CMOS technology Design. Technologies. Operation analysis. Testing DRAM chips Dynamic random access memory Electric, optical and optoelectronic circuits Electronic circuits Electronics equalizers Error correction Exact sciences and technology high-speed integrated circuits Inductors Integrated circuits Integrated circuits by function (including memories and processors) interconnections intersymbol interference Inverters jitter Links Magnetic devices Physical layer Random access memory Regulators Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices synchronization Time measurements Timing transceivers
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