New Observations in LOD Effect of 45-nm P-MOSFETs With Strained SiGe Source/Drain and Dummy Gate
Length of thin oxide definition area (LOD) effects and the incorporation of the dummy poly gates on the performance of 45-nm P-MOSFETs with and without strained SiGe source/drain (S/D) are systematically investigated. In the non-SiGe devices, the LOD effect is dominated by the STI stress and shows a...
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| Veröffentlicht in: | IEEE transactions on electron devices 2009-08, Vol.56 (8), p.1618-1623 |
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| container_title | IEEE transactions on electron devices |
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| creator | Chung-Yun Cheng Yean-Kuen Fang Jang-Cheng Hsieh Sheng-Jier Yang Yi-Ming Sheu Hsia, H. |
| description | Length of thin oxide definition area (LOD) effects and the incorporation of the dummy poly gates on the performance of 45-nm P-MOSFETs with and without strained SiGe source/drain (S/D) are systematically investigated. In the non-SiGe devices, the LOD effect is dominated by the STI stress and shows a little dependence of dummy poly gates. However, in the SiGe device, the LOD effect is strongly dependent on the location of the dummy poly gate. For dummy poly gate located outside the active area, the compressive stress from the SiGe S/D dominates the LOD effect, but for dummy poly gate located within the active area, the LOD effect is controlled by both the SiGe S/D stress within the dummy gate and the STI stress. The mechanisms of our new observations are analyzed with TCAD simulations. |
| doi_str_mv | 10.1109/TED.2009.2022690 |
| format | Article |
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In the non-SiGe devices, the LOD effect is dominated by the STI stress and shows a little dependence of dummy poly gates. However, in the SiGe device, the LOD effect is strongly dependent on the location of the dummy poly gate. For dummy poly gate located outside the active area, the compressive stress from the SiGe S/D dominates the LOD effect, but for dummy poly gate located within the active area, the LOD effect is controlled by both the SiGe S/D stress within the dummy gate and the STI stress. The mechanisms of our new observations are analyzed with TCAD simulations.</description><identifier>ISSN: 0018-9383</identifier><identifier>EISSN: 1557-9646</identifier><identifier>DOI: 10.1109/TED.2009.2022690</identifier><identifier>CODEN: IETDAI</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Active control ; Applied sciences ; Devices ; Distance measurement ; Drains ; Dummies ; Dummy gate ; Electronics ; Exact sciences and technology ; Gates ; I_{\rm dlin} ; I_{\rm dsat} ; Layout ; length of thin oxide definition area (LOD) effect ; Logic gates ; MOSFET circuits ; Oxides ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; SiGe source/drain (S/D) ; Silicon ; Silicon germanides ; Silicon germanium ; STI ; Stress ; Stresses ; Transistors</subject><ispartof>IEEE transactions on electron devices, 2009-08, Vol.56 (8), p.1618-1623</ispartof><rights>2009 INIST-CNRS</rights><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2009</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c352t-8986e8d3b3d52c3bb05832fbdcbe731843563e43d4cf5c817e0f64f8723068973</citedby><cites>FETCH-LOGICAL-c352t-8986e8d3b3d52c3bb05832fbdcbe731843563e43d4cf5c817e0f64f8723068973</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5109722$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27923,27924,54757</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5109722$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=21884640$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Chung-Yun Cheng</creatorcontrib><creatorcontrib>Yean-Kuen Fang</creatorcontrib><creatorcontrib>Jang-Cheng Hsieh</creatorcontrib><creatorcontrib>Sheng-Jier Yang</creatorcontrib><creatorcontrib>Yi-Ming Sheu</creatorcontrib><creatorcontrib>Hsia, H.</creatorcontrib><title>New Observations in LOD Effect of 45-nm P-MOSFETs With Strained SiGe Source/Drain and Dummy Gate</title><title>IEEE transactions on electron devices</title><addtitle>TED</addtitle><description>Length of thin oxide definition area (LOD) effects and the incorporation of the dummy poly gates on the performance of 45-nm P-MOSFETs with and without strained SiGe source/drain (S/D) are systematically investigated. In the non-SiGe devices, the LOD effect is dominated by the STI stress and shows a little dependence of dummy poly gates. However, in the SiGe device, the LOD effect is strongly dependent on the location of the dummy poly gate. For dummy poly gate located outside the active area, the compressive stress from the SiGe S/D dominates the LOD effect, but for dummy poly gate located within the active area, the LOD effect is controlled by both the SiGe S/D stress within the dummy gate and the STI stress. The mechanisms of our new observations are analyzed with TCAD simulations.</description><subject>Active control</subject><subject>Applied sciences</subject><subject>Devices</subject><subject>Distance measurement</subject><subject>Drains</subject><subject>Dummies</subject><subject>Dummy gate</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Gates</subject><subject>I_{\rm dlin}</subject><subject>I_{\rm dsat}</subject><subject>Layout</subject><subject>length of thin oxide definition area (LOD) effect</subject><subject>Logic gates</subject><subject>MOSFET circuits</subject><subject>Oxides</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>SiGe source/drain (S/D)</subject><subject>Silicon</subject><subject>Silicon germanides</subject><subject>Silicon germanium</subject><subject>STI</subject><subject>Stress</subject><subject>Stresses</subject><subject>Transistors</subject><issn>0018-9383</issn><issn>1557-9646</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2009</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpdkM2LFDEQxYMoOK7eBS9BEE-9m--uHGVnnF0YHWFWPMZ0uoJZprvXpEfZ_94MM-zBSxVV9avH4xHylrNLzpm9ulstLwVjthYhjGXPyIJr3TbWKPOcLBjj0FgJ8iV5Vcp9HY1SYkF-fsW_dNsVzH_8nKax0DTSzXZJVzFimOkUqdLNONBvzZft7vPqrtAfaf5Fd3P2acSe7tIa6W465IBXy-OO-rGny8MwPNK1n_E1eRH9vuCbc78g36vK9U2z2a5vrz9tmiC1mBuwYBB62cleiyC7jmmQInZ96LCVHJTURqKSvQpRB-AtsmhUhFZIZsC28oJ8POk-5On3AcvshlQC7vd-xOlQHBgLCrhVlXz_H3lf7Y_VnANtrAAtoELsBIU8lZIxuoecBp8fHWfuGLirgbtj4O4ceH35cNb1Jfh9zH4MqTz9CQ6gjDpy705cQsSns66arRDyH0ujhRs</recordid><startdate>20090801</startdate><enddate>20090801</enddate><creator>Chung-Yun Cheng</creator><creator>Yean-Kuen Fang</creator><creator>Jang-Cheng Hsieh</creator><creator>Sheng-Jier Yang</creator><creator>Yi-Ming Sheu</creator><creator>Hsia, H.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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Microelectronics. Optoelectronics. Solid state devices</topic><topic>SiGe source/drain (S/D)</topic><topic>Silicon</topic><topic>Silicon germanides</topic><topic>Silicon germanium</topic><topic>STI</topic><topic>Stress</topic><topic>Stresses</topic><topic>Transistors</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Chung-Yun Cheng</creatorcontrib><creatorcontrib>Yean-Kuen Fang</creatorcontrib><creatorcontrib>Jang-Cheng Hsieh</creatorcontrib><creatorcontrib>Sheng-Jier Yang</creatorcontrib><creatorcontrib>Yi-Ming Sheu</creatorcontrib><creatorcontrib>Hsia, H.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE transactions on electron devices</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Chung-Yun Cheng</au><au>Yean-Kuen Fang</au><au>Jang-Cheng Hsieh</au><au>Sheng-Jier Yang</au><au>Yi-Ming Sheu</au><au>Hsia, H.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>New Observations in LOD Effect of 45-nm P-MOSFETs With Strained SiGe Source/Drain and Dummy Gate</atitle><jtitle>IEEE transactions on electron devices</jtitle><stitle>TED</stitle><date>2009-08-01</date><risdate>2009</risdate><volume>56</volume><issue>8</issue><spage>1618</spage><epage>1623</epage><pages>1618-1623</pages><issn>0018-9383</issn><eissn>1557-9646</eissn><coden>IETDAI</coden><abstract>Length of thin oxide definition area (LOD) effects and the incorporation of the dummy poly gates on the performance of 45-nm P-MOSFETs with and without strained SiGe source/drain (S/D) are systematically investigated. In the non-SiGe devices, the LOD effect is dominated by the STI stress and shows a little dependence of dummy poly gates. However, in the SiGe device, the LOD effect is strongly dependent on the location of the dummy poly gate. For dummy poly gate located outside the active area, the compressive stress from the SiGe S/D dominates the LOD effect, but for dummy poly gate located within the active area, the LOD effect is controlled by both the SiGe S/D stress within the dummy gate and the STI stress. The mechanisms of our new observations are analyzed with TCAD simulations.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/TED.2009.2022690</doi><tpages>6</tpages></addata></record> |
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| subjects | Active control Applied sciences Devices Distance measurement Drains Dummies Dummy gate Electronics Exact sciences and technology Gates I_{\rm dlin} I_{\rm dsat} Layout length of thin oxide definition area (LOD) effect Logic gates MOSFET circuits Oxides Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices SiGe source/drain (S/D) Silicon Silicon germanides Silicon germanium STI Stress Stresses Transistors |
| title | New Observations in LOD Effect of 45-nm P-MOSFETs With Strained SiGe Source/Drain and Dummy Gate |
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