A 16-bit 250-MS/s IF Sampling Pipelined ADC With Background Calibration

This paper describes a 16-bit 250 MS/s ADC fabricated on a 0.18 BiCMOS process. The ADC has an integrated input buffer with a new linearization technique that improves its distortion by 5-10 dB and lowers its power consumption by 70% relative to the state of the art. It demonstrates a new background...

Ausführliche Beschreibung