0.5-V Low- V rm T CMOS Preamplifier for Low-Power and High-Speed Gigabit-DRAM Arrays

A novel low- V rm T CMOS preamplifier was developed for low-power and high-speed gigabit DRAM arrays. The sensing time of a sense amplifier (SA) with the proposed preamplifier and its activation schemes at a data-line voltage of 0.5 V was 6 ns, which is 62% shorter than that of an SA using a convent...

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Veröffentlicht in:	IEEE journal of solid-state circuits 2010-11, Vol.45 (11), p.2348-2355
Hauptverfasser:	Kotabe, Akira, Yanagawa, Yoshimitsu, Akiyama, Satoru, Sekiguchi, Tomonori
Format:	Artikel
Sprache:	eng
Schlagworte:	Activation Arrays Circuits CMOS Dynamic random access memory Electric potential High speed Preamplifiers Voltage
Online-Zugang:	Volltext
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