0.5-V Low- V rm T CMOS Preamplifier for Low-Power and High-Speed Gigabit-DRAM Arrays
A novel low- V rm T CMOS preamplifier was developed for low-power and high-speed gigabit DRAM arrays. The sensing time of a sense amplifier (SA) with the proposed preamplifier and its activation schemes at a data-line voltage of 0.5 V was 6 ns, which is 62% shorter than that of an SA using a convent...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 2010-11, Vol.45 (11), p.2348-2355 |
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| container_issue | 11 |
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| container_title | IEEE journal of solid-state circuits |
| container_volume | 45 |
| creator | Kotabe, Akira Yanagawa, Yoshimitsu Akiyama, Satoru Sekiguchi, Tomonori |
| description | A novel low- V rm T CMOS preamplifier was developed for low-power and high-speed gigabit DRAM arrays. The sensing time of a sense amplifier (SA) with the proposed preamplifier and its activation schemes at a data-line voltage of 0.5 V was 6 ns, which is 62% shorter than that of an SA using a conventional preamplifier. By activating the proposed preamplifier temporarily during the write cycle, the writing time was 16.3 ns, which is 72% shorter than the case without activation of the proposed preamplifier, and this time is short enough to apply a DRAM array using the proposed preamplifier to 1.6-Gbit/s/pin DDR3 SDRAM. The operating current of the memory array and its peripheral circuit including the proposed preamplifier was reduced by 12% by reducing the data-line voltage from 0.8 to 0.5 V. |
| doi_str_mv | 10.1109/JSSC.2010.2065650 |
| format | Article |
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The sensing time of a sense amplifier (SA) with the proposed preamplifier and its activation schemes at a data-line voltage of 0.5 V was 6 ns, which is 62% shorter than that of an SA using a conventional preamplifier. By activating the proposed preamplifier temporarily during the write cycle, the writing time was 16.3 ns, which is 72% shorter than the case without activation of the proposed preamplifier, and this time is short enough to apply a DRAM array using the proposed preamplifier to 1.6-Gbit/s/pin DDR3 SDRAM. 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| fulltext | fulltext |
| identifier | ISSN: 0018-9200 |
| ispartof | IEEE journal of solid-state circuits, 2010-11, Vol.45 (11), p.2348-2355 |
| issn | 0018-9200 1558-173X |
| language | eng |
| recordid | cdi_proquest_miscellaneous_831174954 |
| source | IEEE Electronic Library (IEL) |
| subjects | Activation Arrays Circuits CMOS Dynamic random access memory Electric potential High speed Preamplifiers Voltage |
| title | 0.5-V Low- V rm T CMOS Preamplifier for Low-Power and High-Speed Gigabit-DRAM Arrays |
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