Fabrication of self-aligned TFTs with a ultra-low temperature polycrystalline silicon process on metal foils
We have fabricated self-aligned thin-film transistors (TFTs) using a ultra-low temperature ( T < 200 °C) polycrystalline silicon process on stainless steel foil substrates. The overall processing scheme and technical details were discussed from the viewpoint of electrical and mechanical stabiliti...
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| Veröffentlicht in: | Solid-state electronics 2010-11, Vol.54 (11), p.1326-1331 |
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| container_title | Solid-state electronics |
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| creator | Moon, Jaehyun Kim, Yong-Hae Park, Dong-Jin Chung, Choong-Heui Kang, Seung-Youl Lee, Jin-Ho |
| description | We have fabricated self-aligned thin-film transistors (TFTs) using a ultra-low temperature (
T
<
200
°C) polycrystalline silicon process on stainless steel foil substrates. The overall processing scheme and technical details were discussed from the viewpoint of electrical and mechanical stabilities. Large grain poly-Si films were obtained with sequential lateral solidification (SLS) method. Plasma enhanced atomic layer deposition (PEALD) method was used to form Al
2O
3 gate dielectric films. The TFT performances were enhanced by plasma oxidation of the polycrystalline Si surface prior to Al
2O
3 gate dielectric film deposition. The fabricated TFT showed a field effect mobility of 95
cm
2/Vs, a threshold voltage of −3
V and a sub-threshold swing of 0.45
V/dec. |
| doi_str_mv | 10.1016/j.sse.2010.05.021 |
| format | Article |
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T
<
200
°C) polycrystalline silicon process on stainless steel foil substrates. The overall processing scheme and technical details were discussed from the viewpoint of electrical and mechanical stabilities. Large grain poly-Si films were obtained with sequential lateral solidification (SLS) method. Plasma enhanced atomic layer deposition (PEALD) method was used to form Al
2O
3 gate dielectric films. The TFT performances were enhanced by plasma oxidation of the polycrystalline Si surface prior to Al
2O
3 gate dielectric film deposition. The fabricated TFT showed a field effect mobility of 95
cm
2/Vs, a threshold voltage of −3
V and a sub-threshold swing of 0.45
V/dec.</description><identifier>ISSN: 0038-1101</identifier><identifier>EISSN: 1879-2405</identifier><identifier>DOI: 10.1016/j.sse.2010.05.021</identifier><language>eng</language><publisher>Kidlington: Elsevier Ltd</publisher><subject>Aluminum oxide ; Applied sciences ; Atomic layer deposition ; Deposition ; Dielectrics ; Electronics ; Exact sciences and technology ; Gates ; Metal foil ; Polycrystalline Si ; Semiconductor devices ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Silicon ; Silicon substrates ; TFT ; Thin film transistors ; Transistors</subject><ispartof>Solid-state electronics, 2010-11, Vol.54 (11), p.1326-1331</ispartof><rights>2010 Elsevier Ltd</rights><rights>2015 INIST-CNRS</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c359t-a8e8b75bc7864d272c61a1d13da1dea5806363237ef195345d1e2e63c03055623</citedby><cites>FETCH-LOGICAL-c359t-a8e8b75bc7864d272c61a1d13da1dea5806363237ef195345d1e2e63c03055623</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://www.sciencedirect.com/science/article/pii/S0038110110001966$$EHTML$$P50$$Gelsevier$$H</linktohtml><link.rule.ids>314,776,780,3537,27901,27902,65306</link.rule.ids><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=23164861$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Moon, Jaehyun</creatorcontrib><creatorcontrib>Kim, Yong-Hae</creatorcontrib><creatorcontrib>Park, Dong-Jin</creatorcontrib><creatorcontrib>Chung, Choong-Heui</creatorcontrib><creatorcontrib>Kang, Seung-Youl</creatorcontrib><creatorcontrib>Lee, Jin-Ho</creatorcontrib><title>Fabrication of self-aligned TFTs with a ultra-low temperature polycrystalline silicon process on metal foils</title><title>Solid-state electronics</title><description>We have fabricated self-aligned thin-film transistors (TFTs) using a ultra-low temperature (
T
<
200
°C) polycrystalline silicon process on stainless steel foil substrates. The overall processing scheme and technical details were discussed from the viewpoint of electrical and mechanical stabilities. Large grain poly-Si films were obtained with sequential lateral solidification (SLS) method. Plasma enhanced atomic layer deposition (PEALD) method was used to form Al
2O
3 gate dielectric films. The TFT performances were enhanced by plasma oxidation of the polycrystalline Si surface prior to Al
2O
3 gate dielectric film deposition. The fabricated TFT showed a field effect mobility of 95
cm
2/Vs, a threshold voltage of −3
V and a sub-threshold swing of 0.45
V/dec.</description><subject>Aluminum oxide</subject><subject>Applied sciences</subject><subject>Atomic layer deposition</subject><subject>Deposition</subject><subject>Dielectrics</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Gates</subject><subject>Metal foil</subject><subject>Polycrystalline Si</subject><subject>Semiconductor devices</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Silicon</subject><subject>Silicon substrates</subject><subject>TFT</subject><subject>Thin film transistors</subject><subject>Transistors</subject><issn>0038-1101</issn><issn>1879-2405</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2010</creationdate><recordtype>article</recordtype><recordid>eNp9kMFuGyEQhlHUSHWTPkBvXKqe1hnAsFg9VVHcRLLUi3tGmJ1tsPDiMriR375YjnLMZWbQfPMz8zP2RcBcgDB3uzkRziW0N-g5SHHFZsL2y04uQH9gMwBlO9HQj-wT0Q4ApBEwY2nltyUGX2OeeB45YRo7n-KfCQe-WW2Iv8T6zD0_plp8l_ILr7g_YPH1WJAfcjqFcqLqU4oTcoophqZ0KDkgEW_lHluTjzkmumXXo0-En1_zDfu9etjcP3brXz-f7n-su6D0snbeot32eht6axaD7GUwwotBqKFF9NqCUUZJ1eMollot9CBQolEBFGhtpLph3y66bY2_R6Tq9pECpuQnzEdyve1lE7HQSHEhQ8lEBUd3KHHvy8kJcGdj3c41Y93ZWAfaNWPbzNdXdU_Bp7H4KUR6G5RKmIU1Z-77hcN26r-IxVGIOAUcYsFQ3ZDjO7_8B0oXjno</recordid><startdate>20101101</startdate><enddate>20101101</enddate><creator>Moon, Jaehyun</creator><creator>Kim, Yong-Hae</creator><creator>Park, Dong-Jin</creator><creator>Chung, Choong-Heui</creator><creator>Kang, Seung-Youl</creator><creator>Lee, Jin-Ho</creator><general>Elsevier Ltd</general><general>Elsevier</general><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7QF</scope><scope>7SP</scope><scope>7U5</scope><scope>8FD</scope><scope>H8D</scope><scope>JG9</scope><scope>L7M</scope></search><sort><creationdate>20101101</creationdate><title>Fabrication of self-aligned TFTs with a ultra-low temperature polycrystalline silicon process on metal foils</title><author>Moon, Jaehyun ; Kim, Yong-Hae ; Park, Dong-Jin ; Chung, Choong-Heui ; Kang, Seung-Youl ; Lee, Jin-Ho</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c359t-a8e8b75bc7864d272c61a1d13da1dea5806363237ef195345d1e2e63c03055623</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2010</creationdate><topic>Aluminum oxide</topic><topic>Applied sciences</topic><topic>Atomic layer deposition</topic><topic>Deposition</topic><topic>Dielectrics</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Gates</topic><topic>Metal foil</topic><topic>Polycrystalline Si</topic><topic>Semiconductor devices</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Silicon</topic><topic>Silicon substrates</topic><topic>TFT</topic><topic>Thin film transistors</topic><topic>Transistors</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Moon, Jaehyun</creatorcontrib><creatorcontrib>Kim, Yong-Hae</creatorcontrib><creatorcontrib>Park, Dong-Jin</creatorcontrib><creatorcontrib>Chung, Choong-Heui</creatorcontrib><creatorcontrib>Kang, Seung-Youl</creatorcontrib><creatorcontrib>Lee, Jin-Ho</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Aluminium Industry Abstracts</collection><collection>Electronics & Communications Abstracts</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>Technology Research Database</collection><collection>Aerospace Database</collection><collection>Materials Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>Solid-state electronics</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Moon, Jaehyun</au><au>Kim, Yong-Hae</au><au>Park, Dong-Jin</au><au>Chung, Choong-Heui</au><au>Kang, Seung-Youl</au><au>Lee, Jin-Ho</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Fabrication of self-aligned TFTs with a ultra-low temperature polycrystalline silicon process on metal foils</atitle><jtitle>Solid-state electronics</jtitle><date>2010-11-01</date><risdate>2010</risdate><volume>54</volume><issue>11</issue><spage>1326</spage><epage>1331</epage><pages>1326-1331</pages><issn>0038-1101</issn><eissn>1879-2405</eissn><abstract>We have fabricated self-aligned thin-film transistors (TFTs) using a ultra-low temperature (
T
<
200
°C) polycrystalline silicon process on stainless steel foil substrates. The overall processing scheme and technical details were discussed from the viewpoint of electrical and mechanical stabilities. Large grain poly-Si films were obtained with sequential lateral solidification (SLS) method. Plasma enhanced atomic layer deposition (PEALD) method was used to form Al
2O
3 gate dielectric films. The TFT performances were enhanced by plasma oxidation of the polycrystalline Si surface prior to Al
2O
3 gate dielectric film deposition. The fabricated TFT showed a field effect mobility of 95
cm
2/Vs, a threshold voltage of −3
V and a sub-threshold swing of 0.45
V/dec.</abstract><cop>Kidlington</cop><pub>Elsevier Ltd</pub><doi>10.1016/j.sse.2010.05.021</doi><tpages>6</tpages></addata></record> |
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| identifier | ISSN: 0038-1101 |
| ispartof | Solid-state electronics, 2010-11, Vol.54 (11), p.1326-1331 |
| issn | 0038-1101 1879-2405 |
| language | eng |
| recordid | cdi_proquest_miscellaneous_787280680 |
| source | Elsevier ScienceDirect Journals |
| subjects | Aluminum oxide Applied sciences Atomic layer deposition Deposition Dielectrics Electronics Exact sciences and technology Gates Metal foil Polycrystalline Si Semiconductor devices Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Silicon Silicon substrates TFT Thin film transistors Transistors |
| title | Fabrication of self-aligned TFTs with a ultra-low temperature polycrystalline silicon process on metal foils |
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