Channel-Stress Enhancement Characteristics for Scaled pMOSFETs by Using Damascene Gate With Top-Cut Compressive Stress Liner and eSiGe

A damascene-gate process enhances the drivability in the shorter gate length region, as compared to a conventional gate-first process for pFETs with compressive stress SiN liners and embedded source/drain SiGe. The origin of the gate length effect for damascene-gate pFETs is studied by using UV-Rama...

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Veröffentlicht in:	IEEE transactions on electron devices 2009-11, Vol.56 (11), p.2778-2784
Hauptverfasser:	Mayuzumi, S., Yamakawa, S., Kosemura, D., Takei, M., Tateshita, Y., Wakabayashi, H., Tsukamoto, M., Ohno, T., Ogura, A., Nagashima, N.
Format:	Artikel
Sprache:	eng
Schlagworte:	Applied sciences Channel stress Channels Compressive properties Compressive stress damascene gate Drains Electronics eSiGe Exact sciences and technology gate last Gates high- k hole mobility Liners Logic gates metal gate Metals Microelectronic fabrication (materials and surfaces technology) Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Silicon Silicon germanides Spectroscopy Strain stress simulation Stresses top-cut stress liner Transistors UV-Raman spectroscopy
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