Design of a 770-MHz, 70-mW, 8-bit Subranging ADC Using Reference Voltage Precharging Architecture

This paper describes a high-speed, low-power CMOS subranging analog-to-digital converter (ADC). A reference voltage precharging architecture and the introduction of a comparator with a built-in threshold voltage in the fine ADC are proposed to reduce the settling time of the reference voltage. A T/H circuit with a body-bias control circuit is employed to reduce distortion at a high sampling rate. Moreover, a V TH generator using a replica of the original comparator is also proposed to compensate for V TH deviation due to the process variations. A test chip was fabricated using 90-nm CMOS technology, and showed a high-sampling rate of 770 MS/s and a low-power consumption of 70 mW.