How to improve intrinsic and extrinsic reliability of vias by process optimization
A systematic study of various processes and their impact on intrinsic reliability has been performed on Cu dual damascene interconnects. The most significant improvement for intrinsic reliability is the ‘break-through’ liner. A strong impact on stressmigration (SM) was revealed using a HDP based SiN...
Gespeichert in:
| Veröffentlicht in: | Microelectronic engineering 2008-10, Vol.85 (10), p.2123-2127 |
|---|---|
| Hauptverfasser: | , , , , |
| Format: | Artikel |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 2127 |
|---|---|
| container_issue | 10 |
| container_start_page | 2123 |
| container_title | Microelectronic engineering |
| container_volume | 85 |
| creator | Penka, Sabine Schulte, Susanne Czekalla, Markus Kriz, Jakob Hommel, Martina |
| description | A systematic study of various processes and their impact on intrinsic reliability has been performed on Cu dual damascene interconnects. The most significant improvement for intrinsic reliability is the ‘break-through’ liner. A strong impact on stressmigration (SM) was revealed using a HDP based SiN deposition on top of Cu lines. Early failures in electromigration (EM) studies are present with insufficient cleaning processes. No reliability impact was detected with different plating and slurry chemistries and liner thickness increase. Extrinsic via reliability is assessed with a special test chip comprising 3E9 via/wafer. High ohmic vias are identified before and after thermal stress. As an example, the failure rates in Cu dual damascene levels with relaxed pitch before and after cleaning optimization are discussed. |
| doi_str_mv | 10.1016/j.mee.2008.06.002 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_cross</sourceid><recordid>TN_cdi_proquest_miscellaneous_35376205</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><els_id>S0167931708003031</els_id><sourcerecordid>35376205</sourcerecordid><originalsourceid>FETCH-LOGICAL-c358t-f3d97ef5a361f84cf79c7c89f30ea9d3ad9b5041431494841a812097c9ba77bc3</originalsourceid><addsrcrecordid>eNp9kM1LxDAQxYMouH78Ad5y0Vtr0rRNgicRv0AQRM8hTScwS9usSV1d_3ojqx49DQ9-783MI-SEs5Iz3p4vyxGgrBhTJWtLxqodsuBKiqJpWrVLFpmRhRZc7pODlJYs65qpBXm6C-90DhTHVQxroDjNEaeEjtqpp_DxqyIMaDsccN7Q4OkabaLdhmaTg5RoWM044qedMUxHZM_bIcHxzzwkLzfXz1d3xcPj7f3V5UPhRKPmwoteS_CNFS33qnZeaied0l4wsLoXttddw2peC17rWtXcKl4xLZ3urJSdE4fkbJubj3h9gzSbEZODYbAThLdkRCNkW7Emg3wLuhhSiuDNKuJo48ZwZr7bM0uT2zPf7RnWmtxe9pz-hNvk7OCjnRymP2PFFBeV0Jm72HKQP10jRJMcwuSgxwhuNn3Af7Z8AalfhYU</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>35376205</pqid></control><display><type>article</type><title>How to improve intrinsic and extrinsic reliability of vias by process optimization</title><source>Elsevier ScienceDirect Journals</source><creator>Penka, Sabine ; Schulte, Susanne ; Czekalla, Markus ; Kriz, Jakob ; Hommel, Martina</creator><creatorcontrib>Penka, Sabine ; Schulte, Susanne ; Czekalla, Markus ; Kriz, Jakob ; Hommel, Martina</creatorcontrib><description>A systematic study of various processes and their impact on intrinsic reliability has been performed on Cu dual damascene interconnects. The most significant improvement for intrinsic reliability is the ‘break-through’ liner. A strong impact on stressmigration (SM) was revealed using a HDP based SiN deposition on top of Cu lines. Early failures in electromigration (EM) studies are present with insufficient cleaning processes. No reliability impact was detected with different plating and slurry chemistries and liner thickness increase. Extrinsic via reliability is assessed with a special test chip comprising 3E9 via/wafer. High ohmic vias are identified before and after thermal stress. As an example, the failure rates in Cu dual damascene levels with relaxed pitch before and after cleaning optimization are discussed.</description><identifier>ISSN: 0167-9317</identifier><identifier>EISSN: 1873-5568</identifier><identifier>DOI: 10.1016/j.mee.2008.06.002</identifier><identifier>CODEN: MIENEF</identifier><language>eng</language><publisher>Amsterdam: Elsevier B.V</publisher><subject>Applied sciences ; Cu interconnect ; Design. Technologies. Operation analysis. Testing ; Electromigration ; Electronics ; Exact sciences and technology ; Integrated circuits ; Microelectronic fabrication (materials and surfaces technology) ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Stressmigration</subject><ispartof>Microelectronic engineering, 2008-10, Vol.85 (10), p.2123-2127</ispartof><rights>2008 Elsevier B.V.</rights><rights>2008 INIST-CNRS</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c358t-f3d97ef5a361f84cf79c7c89f30ea9d3ad9b5041431494841a812097c9ba77bc3</citedby><cites>FETCH-LOGICAL-c358t-f3d97ef5a361f84cf79c7c89f30ea9d3ad9b5041431494841a812097c9ba77bc3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://www.sciencedirect.com/science/article/pii/S0167931708003031$$EHTML$$P50$$Gelsevier$$H</linktohtml><link.rule.ids>309,310,314,776,780,785,786,3537,23909,23910,25118,27901,27902,65306</link.rule.ids><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=20813239$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Penka, Sabine</creatorcontrib><creatorcontrib>Schulte, Susanne</creatorcontrib><creatorcontrib>Czekalla, Markus</creatorcontrib><creatorcontrib>Kriz, Jakob</creatorcontrib><creatorcontrib>Hommel, Martina</creatorcontrib><title>How to improve intrinsic and extrinsic reliability of vias by process optimization</title><title>Microelectronic engineering</title><description>A systematic study of various processes and their impact on intrinsic reliability has been performed on Cu dual damascene interconnects. The most significant improvement for intrinsic reliability is the ‘break-through’ liner. A strong impact on stressmigration (SM) was revealed using a HDP based SiN deposition on top of Cu lines. Early failures in electromigration (EM) studies are present with insufficient cleaning processes. No reliability impact was detected with different plating and slurry chemistries and liner thickness increase. Extrinsic via reliability is assessed with a special test chip comprising 3E9 via/wafer. High ohmic vias are identified before and after thermal stress. As an example, the failure rates in Cu dual damascene levels with relaxed pitch before and after cleaning optimization are discussed.</description><subject>Applied sciences</subject><subject>Cu interconnect</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Electromigration</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Integrated circuits</subject><subject>Microelectronic fabrication (materials and surfaces technology)</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Stressmigration</subject><issn>0167-9317</issn><issn>1873-5568</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2008</creationdate><recordtype>article</recordtype><recordid>eNp9kM1LxDAQxYMouH78Ad5y0Vtr0rRNgicRv0AQRM8hTScwS9usSV1d_3ojqx49DQ9-783MI-SEs5Iz3p4vyxGgrBhTJWtLxqodsuBKiqJpWrVLFpmRhRZc7pODlJYs65qpBXm6C-90DhTHVQxroDjNEaeEjtqpp_DxqyIMaDsccN7Q4OkabaLdhmaTg5RoWM044qedMUxHZM_bIcHxzzwkLzfXz1d3xcPj7f3V5UPhRKPmwoteS_CNFS33qnZeaied0l4wsLoXttddw2peC17rWtXcKl4xLZ3urJSdE4fkbJubj3h9gzSbEZODYbAThLdkRCNkW7Emg3wLuhhSiuDNKuJo48ZwZr7bM0uT2zPf7RnWmtxe9pz-hNvk7OCjnRymP2PFFBeV0Jm72HKQP10jRJMcwuSgxwhuNn3Af7Z8AalfhYU</recordid><startdate>20081001</startdate><enddate>20081001</enddate><creator>Penka, Sabine</creator><creator>Schulte, Susanne</creator><creator>Czekalla, Markus</creator><creator>Kriz, Jakob</creator><creator>Hommel, Martina</creator><general>Elsevier B.V</general><general>Elsevier Science</general><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8BQ</scope><scope>8FD</scope><scope>H8G</scope><scope>JG9</scope><scope>L7M</scope></search><sort><creationdate>20081001</creationdate><title>How to improve intrinsic and extrinsic reliability of vias by process optimization</title><author>Penka, Sabine ; Schulte, Susanne ; Czekalla, Markus ; Kriz, Jakob ; Hommel, Martina</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c358t-f3d97ef5a361f84cf79c7c89f30ea9d3ad9b5041431494841a812097c9ba77bc3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2008</creationdate><topic>Applied sciences</topic><topic>Cu interconnect</topic><topic>Design. Technologies. Operation analysis. Testing</topic><topic>Electromigration</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Integrated circuits</topic><topic>Microelectronic fabrication (materials and surfaces technology)</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Stressmigration</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Penka, Sabine</creatorcontrib><creatorcontrib>Schulte, Susanne</creatorcontrib><creatorcontrib>Czekalla, Markus</creatorcontrib><creatorcontrib>Kriz, Jakob</creatorcontrib><creatorcontrib>Hommel, Martina</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>METADEX</collection><collection>Technology Research Database</collection><collection>Copper Technical Reference Library</collection><collection>Materials Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>Microelectronic engineering</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Penka, Sabine</au><au>Schulte, Susanne</au><au>Czekalla, Markus</au><au>Kriz, Jakob</au><au>Hommel, Martina</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>How to improve intrinsic and extrinsic reliability of vias by process optimization</atitle><jtitle>Microelectronic engineering</jtitle><date>2008-10-01</date><risdate>2008</risdate><volume>85</volume><issue>10</issue><spage>2123</spage><epage>2127</epage><pages>2123-2127</pages><issn>0167-9317</issn><eissn>1873-5568</eissn><coden>MIENEF</coden><abstract>A systematic study of various processes and their impact on intrinsic reliability has been performed on Cu dual damascene interconnects. The most significant improvement for intrinsic reliability is the ‘break-through’ liner. A strong impact on stressmigration (SM) was revealed using a HDP based SiN deposition on top of Cu lines. Early failures in electromigration (EM) studies are present with insufficient cleaning processes. No reliability impact was detected with different plating and slurry chemistries and liner thickness increase. Extrinsic via reliability is assessed with a special test chip comprising 3E9 via/wafer. High ohmic vias are identified before and after thermal stress. As an example, the failure rates in Cu dual damascene levels with relaxed pitch before and after cleaning optimization are discussed.</abstract><cop>Amsterdam</cop><pub>Elsevier B.V</pub><doi>10.1016/j.mee.2008.06.002</doi><tpages>5</tpages></addata></record> |
| fulltext | fulltext |
| identifier | ISSN: 0167-9317 |
| ispartof | Microelectronic engineering, 2008-10, Vol.85 (10), p.2123-2127 |
| issn | 0167-9317 1873-5568 |
| language | eng |
| recordid | cdi_proquest_miscellaneous_35376205 |
| source | Elsevier ScienceDirect Journals |
| subjects | Applied sciences Cu interconnect Design. Technologies. Operation analysis. Testing Electromigration Electronics Exact sciences and technology Integrated circuits Microelectronic fabrication (materials and surfaces technology) Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Stressmigration |
| title | How to improve intrinsic and extrinsic reliability of vias by process optimization |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-28T15%3A27%3A22IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_cross&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=How%20to%20improve%20intrinsic%20and%20extrinsic%20reliability%20of%20vias%20by%20process%20optimization&rft.jtitle=Microelectronic%20engineering&rft.au=Penka,%20Sabine&rft.date=2008-10-01&rft.volume=85&rft.issue=10&rft.spage=2123&rft.epage=2127&rft.pages=2123-2127&rft.issn=0167-9317&rft.eissn=1873-5568&rft.coden=MIENEF&rft_id=info:doi/10.1016/j.mee.2008.06.002&rft_dat=%3Cproquest_cross%3E35376205%3C/proquest_cross%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=35376205&rft_id=info:pmid/&rft_els_id=S0167931708003031&rfr_iscdi=true |