Design of a Multimode QC-LDPC Decoder Based on Shift-Routing Network
A reconfigurable message-passing network is proposed to facilitate message transportation in decoding multimode quasi-cyclic low-density parity-check (QC-LDPC) codes. By exploiting the shift-routing network (SRN) features, the decoding messages are routed in parallel to fully support those specific...
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| Veröffentlicht in: | IEEE transactions on circuits and systems. II, Express briefs Express briefs, 2009-09, Vol.56 (9), p.734-738 |
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| container_title | IEEE transactions on circuits and systems. II, Express briefs |
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| creator | Liu, Chih-Hao Lin, Chien-Ching Yen, Shau-Wei Chen, Chih-Lung Chang, Hsie-Chia Lee, Chen-Yi Hsu, Yar-Sun Jou, Shyh-Jye |
| description | A reconfigurable message-passing network is proposed to facilitate message transportation in decoding multimode quasi-cyclic low-density parity-check (QC-LDPC) codes. By exploiting the shift-routing network (SRN) features, the decoding messages are routed in parallel to fully support those specific 19 and 3 submatrix sizes defined in IEEE 802.16e and IEEE 802.11n applications with less hardware complexity. A 6.22- mm 2 QC-LDPC decoder with SRN is implemented in a 90-nm 1-Poly 9-Metal (1P9M) CMOS process. Postlayout simulation results show that the operation frequency can achieve 300 MHz, which is sufficient to process the 212-Mb/s 2304-bit and 178-Mb/s 1944-bit codeword streams for IEEE 802.16e and IEEE 802.11n systems, respectively. |
| doi_str_mv | 10.1109/TCSII.2009.2027967 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_proquest_miscellaneous_34971470</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>5233880</ieee_id><sourcerecordid>875042769</sourcerecordid><originalsourceid>FETCH-LOGICAL-c357t-5402b40a2971a85fdee53bf998a305547b59e22256ff1c52a5ce73caba8a7443</originalsourceid><addsrcrecordid>eNp9kMtOwzAQRSMEEqXwA7CxWMAqxc86XkLCo1J5tnvLTcclkMbFToT4e1xasWDBxuORzh3NnCQ5JnhACFYX03wyGg0oxio-VKqh3El6RIgsZVKR3fWfq1RKLveTgxDeMKYKM9pLigJCtWiQs8ig-65uq6WbA3rO03HxlKMCyth6dGUCzJFr0OS1sm364rq2ahboAdpP598Pkz1r6gBH29pPpjfX0_wuHT_ejvLLcVoyIdtUcExnHBuqJDGZsHMAwWZWqcwwLASXM6GAUiqG1pJSUCNKkKw0M5MZyTnrJ-ebsSvvPjoIrV5WoYS6Ng24LuhMCsypHKpInv1LMh5X4BJH8PQP-OY638QjtCKUyYxhGiG6gUrvQvBg9cpXS-O_NMF6rV__6Ndr_XqrP4ZONqEKAH4DgjKWZZh9AyvKfi4</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>912378302</pqid></control><display><type>article</type><title>Design of a Multimode QC-LDPC Decoder Based on Shift-Routing Network</title><source>IEEE Electronic Library (IEL)</source><creator>Liu, Chih-Hao ; Lin, Chien-Ching ; Yen, Shau-Wei ; Chen, Chih-Lung ; Chang, Hsie-Chia ; Lee, Chen-Yi ; Hsu, Yar-Sun ; Jou, Shyh-Jye</creator><creatorcontrib>Liu, Chih-Hao ; Lin, Chien-Ching ; Yen, Shau-Wei ; Chen, Chih-Lung ; Chang, Hsie-Chia ; Lee, Chen-Yi ; Hsu, Yar-Sun ; Jou, Shyh-Jye</creatorcontrib><description>A reconfigurable message-passing network is proposed to facilitate message transportation in decoding multimode quasi-cyclic low-density parity-check (QC-LDPC) codes. By exploiting the shift-routing network (SRN) features, the decoding messages are routed in parallel to fully support those specific 19 and 3 submatrix sizes defined in IEEE 802.16e and IEEE 802.11n applications with less hardware complexity. A 6.22- mm 2 QC-LDPC decoder with SRN is implemented in a 90-nm 1-Poly 9-Metal (1P9M) CMOS process. Postlayout simulation results show that the operation frequency can achieve 300 MHz, which is sufficient to process the 212-Mb/s 2304-bit and 178-Mb/s 1944-bit codeword streams for IEEE 802.16e and IEEE 802.11n systems, respectively.</description><identifier>ISSN: 1549-7747</identifier><identifier>EISSN: 1558-3791</identifier><identifier>DOI: 10.1109/TCSII.2009.2027967</identifier><identifier>CODEN: ICSPE5</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Architecture ; Circuits ; CMOS ; CMOS process ; Decoders ; Decoding ; Frequency ; Hardware ; IEEE 802.11n ; IEEE 802.16e ; Matrix decomposition ; message passing ; Messages ; network ; Networks ; Parity check codes ; quasi-cyclic low-density parity check (QC-LDPC) ; Routing ; Sparse matrices ; Switches ; Transportation ; WiMax</subject><ispartof>IEEE transactions on circuits and systems. II, Express briefs, 2009-09, Vol.56 (9), p.734-738</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2009</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c357t-5402b40a2971a85fdee53bf998a305547b59e22256ff1c52a5ce73caba8a7443</citedby><cites>FETCH-LOGICAL-c357t-5402b40a2971a85fdee53bf998a305547b59e22256ff1c52a5ce73caba8a7443</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5233880$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27903,27904,54735</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5233880$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Liu, Chih-Hao</creatorcontrib><creatorcontrib>Lin, Chien-Ching</creatorcontrib><creatorcontrib>Yen, Shau-Wei</creatorcontrib><creatorcontrib>Chen, Chih-Lung</creatorcontrib><creatorcontrib>Chang, Hsie-Chia</creatorcontrib><creatorcontrib>Lee, Chen-Yi</creatorcontrib><creatorcontrib>Hsu, Yar-Sun</creatorcontrib><creatorcontrib>Jou, Shyh-Jye</creatorcontrib><title>Design of a Multimode QC-LDPC Decoder Based on Shift-Routing Network</title><title>IEEE transactions on circuits and systems. II, Express briefs</title><addtitle>TCSII</addtitle><description>A reconfigurable message-passing network is proposed to facilitate message transportation in decoding multimode quasi-cyclic low-density parity-check (QC-LDPC) codes. By exploiting the shift-routing network (SRN) features, the decoding messages are routed in parallel to fully support those specific 19 and 3 submatrix sizes defined in IEEE 802.16e and IEEE 802.11n applications with less hardware complexity. A 6.22- mm 2 QC-LDPC decoder with SRN is implemented in a 90-nm 1-Poly 9-Metal (1P9M) CMOS process. Postlayout simulation results show that the operation frequency can achieve 300 MHz, which is sufficient to process the 212-Mb/s 2304-bit and 178-Mb/s 1944-bit codeword streams for IEEE 802.16e and IEEE 802.11n systems, respectively.</description><subject>Architecture</subject><subject>Circuits</subject><subject>CMOS</subject><subject>CMOS process</subject><subject>Decoders</subject><subject>Decoding</subject><subject>Frequency</subject><subject>Hardware</subject><subject>IEEE 802.11n</subject><subject>IEEE 802.16e</subject><subject>Matrix decomposition</subject><subject>message passing</subject><subject>Messages</subject><subject>network</subject><subject>Networks</subject><subject>Parity check codes</subject><subject>quasi-cyclic low-density parity check (QC-LDPC)</subject><subject>Routing</subject><subject>Sparse matrices</subject><subject>Switches</subject><subject>Transportation</subject><subject>WiMax</subject><issn>1549-7747</issn><issn>1558-3791</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2009</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNp9kMtOwzAQRSMEEqXwA7CxWMAqxc86XkLCo1J5tnvLTcclkMbFToT4e1xasWDBxuORzh3NnCQ5JnhACFYX03wyGg0oxio-VKqh3El6RIgsZVKR3fWfq1RKLveTgxDeMKYKM9pLigJCtWiQs8ig-65uq6WbA3rO03HxlKMCyth6dGUCzJFr0OS1sm364rq2ahboAdpP598Pkz1r6gBH29pPpjfX0_wuHT_ejvLLcVoyIdtUcExnHBuqJDGZsHMAwWZWqcwwLASXM6GAUiqG1pJSUCNKkKw0M5MZyTnrJ-ebsSvvPjoIrV5WoYS6Ng24LuhMCsypHKpInv1LMh5X4BJH8PQP-OY638QjtCKUyYxhGiG6gUrvQvBg9cpXS-O_NMF6rV__6Ndr_XqrP4ZONqEKAH4DgjKWZZh9AyvKfi4</recordid><startdate>20090901</startdate><enddate>20090901</enddate><creator>Liu, Chih-Hao</creator><creator>Lin, Chien-Ching</creator><creator>Yen, Shau-Wei</creator><creator>Chen, Chih-Lung</creator><creator>Chang, Hsie-Chia</creator><creator>Lee, Chen-Yi</creator><creator>Hsu, Yar-Sun</creator><creator>Jou, Shyh-Jye</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>F28</scope><scope>FR3</scope></search><sort><creationdate>20090901</creationdate><title>Design of a Multimode QC-LDPC Decoder Based on Shift-Routing Network</title><author>Liu, Chih-Hao ; Lin, Chien-Ching ; Yen, Shau-Wei ; Chen, Chih-Lung ; Chang, Hsie-Chia ; Lee, Chen-Yi ; Hsu, Yar-Sun ; Jou, Shyh-Jye</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c357t-5402b40a2971a85fdee53bf998a305547b59e22256ff1c52a5ce73caba8a7443</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2009</creationdate><topic>Architecture</topic><topic>Circuits</topic><topic>CMOS</topic><topic>CMOS process</topic><topic>Decoders</topic><topic>Decoding</topic><topic>Frequency</topic><topic>Hardware</topic><topic>IEEE 802.11n</topic><topic>IEEE 802.16e</topic><topic>Matrix decomposition</topic><topic>message passing</topic><topic>Messages</topic><topic>network</topic><topic>Networks</topic><topic>Parity check codes</topic><topic>quasi-cyclic low-density parity check (QC-LDPC)</topic><topic>Routing</topic><topic>Sparse matrices</topic><topic>Switches</topic><topic>Transportation</topic><topic>WiMax</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Liu, Chih-Hao</creatorcontrib><creatorcontrib>Lin, Chien-Ching</creatorcontrib><creatorcontrib>Yen, Shau-Wei</creatorcontrib><creatorcontrib>Chen, Chih-Lung</creatorcontrib><creatorcontrib>Chang, Hsie-Chia</creatorcontrib><creatorcontrib>Lee, Chen-Yi</creatorcontrib><creatorcontrib>Hsu, Yar-Sun</creatorcontrib><creatorcontrib>Jou, Shyh-Jye</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE transactions on circuits and systems. II, Express briefs</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Liu, Chih-Hao</au><au>Lin, Chien-Ching</au><au>Yen, Shau-Wei</au><au>Chen, Chih-Lung</au><au>Chang, Hsie-Chia</au><au>Lee, Chen-Yi</au><au>Hsu, Yar-Sun</au><au>Jou, Shyh-Jye</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Design of a Multimode QC-LDPC Decoder Based on Shift-Routing Network</atitle><jtitle>IEEE transactions on circuits and systems. II, Express briefs</jtitle><stitle>TCSII</stitle><date>2009-09-01</date><risdate>2009</risdate><volume>56</volume><issue>9</issue><spage>734</spage><epage>738</epage><pages>734-738</pages><issn>1549-7747</issn><eissn>1558-3791</eissn><coden>ICSPE5</coden><abstract>A reconfigurable message-passing network is proposed to facilitate message transportation in decoding multimode quasi-cyclic low-density parity-check (QC-LDPC) codes. By exploiting the shift-routing network (SRN) features, the decoding messages are routed in parallel to fully support those specific 19 and 3 submatrix sizes defined in IEEE 802.16e and IEEE 802.11n applications with less hardware complexity. A 6.22- mm 2 QC-LDPC decoder with SRN is implemented in a 90-nm 1-Poly 9-Metal (1P9M) CMOS process. Postlayout simulation results show that the operation frequency can achieve 300 MHz, which is sufficient to process the 212-Mb/s 2304-bit and 178-Mb/s 1944-bit codeword streams for IEEE 802.16e and IEEE 802.11n systems, respectively.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TCSII.2009.2027967</doi><tpages>5</tpages></addata></record> |
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| subjects | Architecture Circuits CMOS CMOS process Decoders Decoding Frequency Hardware IEEE 802.11n IEEE 802.16e Matrix decomposition message passing Messages network Networks Parity check codes quasi-cyclic low-density parity check (QC-LDPC) Routing Sparse matrices Switches Transportation WiMax |
| title | Design of a Multimode QC-LDPC Decoder Based on Shift-Routing Network |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-28T09%3A20%3A55IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Design%20of%20a%20Multimode%20QC-LDPC%20Decoder%20Based%20on%20Shift-Routing%20Network&rft.jtitle=IEEE%20transactions%20on%20circuits%20and%20systems.%20II,%20Express%20briefs&rft.au=Liu,%20Chih-Hao&rft.date=2009-09-01&rft.volume=56&rft.issue=9&rft.spage=734&rft.epage=738&rft.pages=734-738&rft.issn=1549-7747&rft.eissn=1558-3791&rft.coden=ICSPE5&rft_id=info:doi/10.1109/TCSII.2009.2027967&rft_dat=%3Cproquest_RIE%3E875042769%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=912378302&rft_id=info:pmid/&rft_ieee_id=5233880&rfr_iscdi=true |