Energy and switch area optimizations for FPGA global routing architectures

Energy and switch area optimizations for FPGA global routing architectures

Low energy and small switch area usage are two important design objectives in FPGA global routing architecture design. This article presents an improved MCF model based CAD flow that performs aggressive optimizations, such as topology and wire style optimization, to reduce the energy and switch area...

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Veröffentlicht in:ACM transactions on design automation of electronic systems 2009-01, Vol.14 (1), p.1-25
Hauptverfasser: Zhu, Yi, Hu, Yuanfang, Taylor, Michael B., Cheng, Chung-Kuan
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creator Zhu, Yi
Hu, Yuanfang
Taylor, Michael B.
Cheng, Chung-Kuan
description Low energy and small switch area usage are two important design objectives in FPGA global routing architecture design. This article presents an improved MCF model based CAD flow that performs aggressive optimizations, such as topology and wire style optimization, to reduce the energy and switch area of FPGA global routing architectures. The experiments show that when compared to traditional mesh architecture, the optimized FPGA routing architectures achieve up to 10% to 15% energy savings and up to 20% switch area savings in average for a set of seven benchmark circuits.
doi_str_mv 10.1145/1455229.1455242
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title Energy and switch area optimizations for FPGA global routing architectures
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