Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication

The on-chip communication architecture is a primary determinant of overall performance in complex system-on-chip (SoC) designs. Since the communication requirements of SoC components can vary significantly over time, communication architectures that dynamically detect and adapt to such variations ca...

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Veröffentlicht in:	IEEE transactions on very large scale integration (VLSI) systems 2008-10, Vol.16 (10), p.1413-1426
Hauptverfasser:	Sekar, K., Lahiri, K., Raghunathan, A., Dey, S.
Format:	Artikel
Sprache:	eng
Schlagworte:	3G mobile communication Applied sciences Architecture Bridges Buses (vehicles) Circuit properties Communication architectures Communication system control Communication systems Decoding Design engineering Design. Technologies. Operation analysis. Testing Dynamical systems Dynamics Electric, optical and optoelectronic circuits Electronic circuits Electronic equipment and fabrication. Passive components, printed wiring boards, connectics Electronics Exact sciences and technology high-performance communication Integrated circuits Integrated circuits by function (including memories and processors) on-chip buses Performance analysis Runtime Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Signal convertors System performance System-on-a-chip system-on-chip (SoC) Timing Topology Very large scale integration
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