Innovative power gating for leakage reduction
Leakage has become one of the most dominant factors of power management and signal integrity of nanometer scale integrated circuits. Recently, power gating structures has proven to be effective in controlling leakage. In this paper an alternative dual-V th reduced power gating structure is proposed...
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| creator | Chowdhury, Masud H. Gjanci, Juliana Khaled, Pervez |
| description | Leakage has become one of the most dominant factors of power management and signal integrity of nanometer scale integrated circuits. Recently, power gating structures has proven to be effective in controlling leakage. In this paper an alternative dual-V th reduced power gating structure is proposed for better reduction of leakage currents, especially for low-power, high-performance portable devices. The proposed technique maintains an intermediate power saving state as well as the conventional power cut-off state. The experimental results have demonstrated that the proposed technique can significantly reduce leakage current and associated power consumptions during the HOLD and CUT-OFF power saving modes. |
| doi_str_mv | 10.1109/ISCAS.2008.4541731 |
| format | Conference Proceeding |
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| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 0271-4302 |
| ispartof | 2008 IEEE International Symposium on Circuits and Systems, 2008, p.1568-1571 |
| issn | 0271-4302 2158-1525 |
| language | eng |
| recordid | cdi_proquest_miscellaneous_34524233 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | CMOS logic circuits CMOS technology Delay Energy consumption Gate leakage Leakage current Logic circuits Network-on-a-chip Power engineering computing Threshold voltage |
| title | Innovative power gating for leakage reduction |
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