Design Tradeoffs and Hardware Architecture for Real-Time Iterative MIMO Detection using Sphere Decoding and LDPC Coding

We explore the performance and hardware complexity tradeoffs associated with performing iterative multiple- input multiple-output (MIMO) detection using a sphere decoder and a low-density parity-check (LDPC) decoder. Iterations are performed both within the LDPC decoder as well as via an outer itera...

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Veröffentlicht in:	IEEE journal on selected areas in communications 2008-08, Vol.26 (6), p.1003-1014
Hauptverfasser:	Hyungjin Kim, Lee, D.-U., Villasenor, J.D.
Format:	Artikel
Sprache:	eng
Schlagworte:	CMOS process Detectors Field programmable gate arrays Hardware Iterative decoding Maximum likelihood decoding MIMO Parity check codes Quadrature phase shift keying Throughput
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