Comprehensive Behavioral Modeling of Conventional and Dual-Tuning PLLs
This paper presents a modular and comprehensive nonlinear time-domain behavioral model for phase-locked loops (PLLs) that are suitable for analyzing the impact on the output signal of the noise contribution and nonidealities of the constituent building blocks. The model building blocks are described...
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| Veröffentlicht in: | IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2008-07, Vol.55 (6), p.1628-1638 |
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| container_title | IEEE transactions on circuits and systems. I, Regular papers |
| container_volume | 55 |
| creator | Bizjak, L. Da Dalt, N. Thurner, P. Nonis, R. Palestri, P. Selmi, L. |
| description | This paper presents a modular and comprehensive nonlinear time-domain behavioral model for phase-locked loops (PLLs) that are suitable for analyzing the impact on the output signal of the noise contribution and nonidealities of the constituent building blocks. The model building blocks are described by Simulink submodels and can be configured to implement different PLL topologies. Postprocessing of the PLL output provides the PLL phase noise and spur-to-carrier-ratio performances. The calculated phase-noise spectra are compared with those obtained with the well-known linear model and with measurements. To show the flexibility of this approach, many case studies are reported; among them, the analysis of the spurs due to charge pump mismatch and the transient phase noise, and spurs performances of a PLL featuring a dual control of the voltage-controlled oscillator. |
| doi_str_mv | 10.1109/TCSI.2008.916700 |
| format | Article |
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I, Regular papers</title><addtitle>TCSI</addtitle><description>This paper presents a modular and comprehensive nonlinear time-domain behavioral model for phase-locked loops (PLLs) that are suitable for analyzing the impact on the output signal of the noise contribution and nonidealities of the constituent building blocks. The model building blocks are described by Simulink submodels and can be configured to implement different PLL topologies. Postprocessing of the PLL output provides the PLL phase noise and spur-to-carrier-ratio performances. The calculated phase-noise spectra are compared with those obtained with the well-known linear model and with measurements. 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(IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>F28</scope><scope>FR3</scope></search><sort><creationdate>20080701</creationdate><title>Comprehensive Behavioral Modeling of Conventional and Dual-Tuning PLLs</title><author>Bizjak, L. ; Da Dalt, N. ; Thurner, P. ; Nonis, R. ; Palestri, P. ; Selmi, L.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c353t-e26d66736279c124c90d90ab5467417ca58faf9cb637114268321aec8f6387b53</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2008</creationdate><topic>Charge pumps</topic><topic>Circuit modeling</topic><topic>circuit simulation</topic><topic>Circuits</topic><topic>Flexibility</topic><topic>frequency synthesizers</topic><topic>Mathematical models</topic><topic>Modular</topic><topic>Noise</topic><topic>nonlinear circuits</topic><topic>Nonlinearity</topic><topic>Performance analysis</topic><topic>Phase locked loops</topic><topic>Phase measurement</topic><topic>Phase noise</topic><topic>phase-locked loops (PLLs)</topic><topic>Signal analysis</topic><topic>Time domain analysis</topic><topic>Topology</topic><topic>Transient analysis</topic><topic>Voltage control</topic><topic>voltage-controlled oscillators (VCOs)</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Bizjak, L.</creatorcontrib><creatorcontrib>Da Dalt, N.</creatorcontrib><creatorcontrib>Thurner, P.</creatorcontrib><creatorcontrib>Nonis, R.</creatorcontrib><creatorcontrib>Palestri, P.</creatorcontrib><creatorcontrib>Selmi, L.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE transactions on circuits and systems. I, Regular papers</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Bizjak, L.</au><au>Da Dalt, N.</au><au>Thurner, P.</au><au>Nonis, R.</au><au>Palestri, P.</au><au>Selmi, L.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Comprehensive Behavioral Modeling of Conventional and Dual-Tuning PLLs</atitle><jtitle>IEEE transactions on circuits and systems. I, Regular papers</jtitle><stitle>TCSI</stitle><date>2008-07-01</date><risdate>2008</risdate><volume>55</volume><issue>6</issue><spage>1628</spage><epage>1638</epage><pages>1628-1638</pages><issn>1549-8328</issn><eissn>1558-0806</eissn><coden>ITCSCH</coden><abstract>This paper presents a modular and comprehensive nonlinear time-domain behavioral model for phase-locked loops (PLLs) that are suitable for analyzing the impact on the output signal of the noise contribution and nonidealities of the constituent building blocks. The model building blocks are described by Simulink submodels and can be configured to implement different PLL topologies. Postprocessing of the PLL output provides the PLL phase noise and spur-to-carrier-ratio performances. The calculated phase-noise spectra are compared with those obtained with the well-known linear model and with measurements. To show the flexibility of this approach, many case studies are reported; among them, the analysis of the spurs due to charge pump mismatch and the transient phase noise, and spurs performances of a PLL featuring a dual control of the voltage-controlled oscillator.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TCSI.2008.916700</doi><tpages>11</tpages></addata></record> |
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| ispartof | IEEE transactions on circuits and systems. I, Regular papers, 2008-07, Vol.55 (6), p.1628-1638 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Charge pumps Circuit modeling circuit simulation Circuits Flexibility frequency synthesizers Mathematical models Modular Noise nonlinear circuits Nonlinearity Performance analysis Phase locked loops Phase measurement Phase noise phase-locked loops (PLLs) Signal analysis Time domain analysis Topology Transient analysis Voltage control voltage-controlled oscillators (VCOs) |
| title | Comprehensive Behavioral Modeling of Conventional and Dual-Tuning PLLs |
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