Timing verification by formal signal interaction modeling in a multi-level timing simulator
A new multi-level macromodeling technique for timing simulation has been developed. This technique is based upon the modeling of the behavior of subcircuits under single input changes. The possible interactions between multiple input changes determine the range of validity of the models. A formal me...
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| creator | Benkoski, J. Strojwas, A. J. |
| description | A new multi-level macromodeling technique for timing simulation has been developed. This technique is based upon the modeling of the behavior of subcircuits under single input changes. The possible interactions between multiple input changes determine the range of validity of the models. A formal method for developing the model validity conditions is presented. This work establishes a bridge between timing analysis by using single input change models, and timing simulation which correctly models signal interactions. The availability of a formal criterion for the validity of the models allows the dynamic identification of the parts of the circuit that require more accurate models. As a result, the cost advantage of high level models can be fully exploited while still allowing critical interactions to be simulated with high accuracy. |
| doi_str_mv | 10.1145/74382.74500 |
| format | Conference Proceeding |
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As a result, the cost advantage of high level models can be fully exploited while still allowing critical interactions to be simulated with high accuracy.</description><subject>Analytical models</subject><subject>Bridge circuits</subject><subject>Circuit simulation</subject><subject>Computational modeling</subject><subject>Computer simulation</subject><subject>Costs</subject><subject>Hardware -- Hardware validation -- Functional verification</subject><subject>Hardware -- Hardware validation -- Functional verification -- Simulation and emulation</subject><subject>Hardware -- Very large scale integration design</subject><subject>Permission</subject><subject>Propagation delay</subject><subject>Signal analysis</subject><subject>Timing</subject><issn>0738-100X</issn><isbn>0897913108</isbn><isbn>9780897913102</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1989</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNqNkEtLAzEUhQMqWGtXLt3MQlwIU28mmTyWUnxBwU0FwUXIpHdKNDOpk2mh_95p6w_wbg7c852zOIRcUZhSyst7yZkqppKXACfkApSWmjIK6pSMQDKVU4CPczJJ6QuG40xozkfkc-Eb366yLXa-9s72PrZZtcvq2DU2ZMmv2kF822Nn3cFs4hLDPuLbzGbNJvQ-D7jFkPXHquSHp-1jd0nOahsSTv50TN6fHhezl3z-9vw6e5jnthAF5FJr5LYChU5L0MpZ6ZwTKAWtBFdMVLyoGdMg0LJiSUspmeNO8aVkBWhgY3J77F138WeDqTeNTw5DsC3GTTKMCqYAigG8PoIeEc26843tdoaWSnAhBvfu6FrXmCrG72QomP225rCtOWxrqs5jPcA3_4DZL5jJdik</recordid><startdate>19890601</startdate><enddate>19890601</enddate><creator>Benkoski, J.</creator><creator>Strojwas, A. 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J.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Timing verification by formal signal interaction modeling in a multi-level timing simulator</atitle><btitle>26th ACM/IEEE Design Automation Conference</btitle><stitle>DAC</stitle><date>1989-06-01</date><risdate>1989</risdate><spage>668</spage><epage>673</epage><pages>668-673</pages><issn>0738-100X</issn><isbn>0897913108</isbn><isbn>9780897913102</isbn><abstract>A new multi-level macromodeling technique for timing simulation has been developed. This technique is based upon the modeling of the behavior of subcircuits under single input changes. The possible interactions between multiple input changes determine the range of validity of the models. A formal method for developing the model validity conditions is presented. This work establishes a bridge between timing analysis by using single input change models, and timing simulation which correctly models signal interactions. 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| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 0738-100X |
| ispartof | 26th ACM/IEEE Design Automation Conference, 1989, p.668-673 |
| issn | 0738-100X |
| language | eng |
| recordid | cdi_proquest_miscellaneous_31638002 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Analytical models Bridge circuits Circuit simulation Computational modeling Computer simulation Costs Hardware -- Hardware validation -- Functional verification Hardware -- Hardware validation -- Functional verification -- Simulation and emulation Hardware -- Very large scale integration design Permission Propagation delay Signal analysis Timing |
| title | Timing verification by formal signal interaction modeling in a multi-level timing simulator |
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