The ZS-1 central processor
The Astronautics ZS-1 is a high speed, 64-bit computer system designed for scientific and engineering applications. The ZS-1 central processor uses a decoupled architecture, which splits instructions into two streams---one for fixed point/memory address computation and the other for floating point o...
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| creator | Smith, J. E. Dermer, G. E. Vanderwarn, B. D. Klinger, S. D. Rozewski, C. M. Fowler, D. L. Scidmore, K. R. Laudon, J. P. |
| description | The Astronautics ZS-1 is a high speed, 64-bit computer system designed for scientific and engineering applications. The ZS-1 central processor uses a decoupled architecture, which splits instructions into two streams---one for fixed point/memory address computation and the other for floating point operations. The two instruction streams are then processed in parallel. Pipelining is also used extensively throughout the ZS-1.This paper describes the architecture and implementation of the ZS-1 central processor, beginning with some of the basic design objectives. Descriptions of the instruction set, pipeline structure, and virtual memory implementation demonstrate the methods used to satisfy the objectives. High performance is achieved through a combination of static (compile-time) instruction scheduling and dynamic (run-time) scheduling. Both types of scheduling are illustrated with examples. |
| doi_str_mv | 10.1145/36206.36203 |
| format | Conference Proceeding |
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E. ; Dermer, G. E. ; Vanderwarn, B. D. ; Klinger, S. D. ; Rozewski, C. M. ; Fowler, D. L. ; Scidmore, K. R. ; Laudon, J. P.</creator><contributor>Katz, Randy</contributor><creatorcontrib>Smith, J. E. ; Dermer, G. E. ; Vanderwarn, B. D. ; Klinger, S. D. ; Rozewski, C. M. ; Fowler, D. L. ; Scidmore, K. R. ; Laudon, J. P. ; Katz, Randy</creatorcontrib><description>The Astronautics ZS-1 is a high speed, 64-bit computer system designed for scientific and engineering applications. The ZS-1 central processor uses a decoupled architecture, which splits instructions into two streams---one for fixed point/memory address computation and the other for floating point operations. The two instruction streams are then processed in parallel. Pipelining is also used extensively throughout the ZS-1.This paper describes the architecture and implementation of the ZS-1 central processor, beginning with some of the basic design objectives. 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P.</au><au>Katz, Randy</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>The ZS-1 central processor</atitle><btitle>Computer architecture news</btitle><date>1987</date><risdate>1987</risdate><spage>199</spage><epage>204</epage><pages>199-204</pages><issn>0163-5964</issn><isbn>0818608056</isbn><isbn>9780818608056</isbn><abstract>The Astronautics ZS-1 is a high speed, 64-bit computer system designed for scientific and engineering applications. The ZS-1 central processor uses a decoupled architecture, which splits instructions into two streams---one for fixed point/memory address computation and the other for floating point operations. The two instruction streams are then processed in parallel. Pipelining is also used extensively throughout the ZS-1.This paper describes the architecture and implementation of the ZS-1 central processor, beginning with some of the basic design objectives. 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| fulltext | fulltext |
| identifier | ISSN: 0163-5964 |
| ispartof | Computer architecture news, 1987, p.199-204 |
| issn | 0163-5964 |
| language | eng |
| recordid | cdi_proquest_miscellaneous_31637045 |
| source | ACM Digital Library |
| subjects | Applied computing -- Computers in other domains -- Personal computers and PC applications Applied computing -- Physical sciences and engineering Computer systems organization -- Architectures Computer systems organization -- Dependable and fault-tolerant systems and networks General and reference -- Cross-computing tools and techniques -- Performance Networks -- Network performance evaluation |
| title | The ZS-1 central processor |
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